Can (controller area network) bus is one of the field bus, which is designed by Bosch Company of Germany for the monitoring and control system of automobile. It is suitable for the interconnection between industrial process control equipment and monitoring equipment. It is a multi master serial communication bus. The basic design specification requires high bit rate, high anti electromagnetic interference, and can detect any errors. It is mainly used in automobile electric control system, elevator control system, safety monitoring system, medical instrument, textile machinery, ship transportation, etc. Can has the following main characteristics: (1) low cost; ② Long distance transmission (up to LKM); ③ High speed data transmission rate (up to 1mbit / s); ④ The message can be received or shielded according to its ID; ⑤ Reliable error handling and detection mechanism; ⑥ When the message is destroyed, it can be automatically retransmitted; ⑦ In case of serious error, the node can exit the bus automatically.

  Can interface circuit of embedded system

The can interface hardware module of embedded system based on ARM7 architecture includes embedded microprocessor S3C44BOX of SamSung company, can controller chip sjal000 of Philips company and can bus transceiver PCA82C250. 8KB cache and Samsung S3C44BOX microprocessor are cost-effective and high-performance microcontroller solutions provided by SamSung company for handheld devices and general applications. They use ARM7TDMI CPU core and work at 66MHz. In order to reduce the total system cost and peripheral devices, the chip also integrates the following components: external memory controller, LCD controller, 4 DMA channels, 2-channel asynchronous UART unit, 1 synchronous serial port (SIO), 1 Multi master 12C bus controller, 1 is bus controller, 5-channel PWM timer and an internal timer, 71 general-purpose I / O ports 8 external interrupt sources, real-time clock, 8-Channel 10 bit ADC, etc.

  can bus controller

Sjal000 of Philips company is selected as can bus controller. Sjal000 is an independent controller, which is used for controller area network (can) in automobile and general industrial environment. It is an alternative product of Philips semiconductor pca82c200 can controller (basic can). Moreover, it adds a new working mode (Pelican), which supports CAN2.0B protocol with many new features. SJA1000 is a new generation of CAN controller, which has the following characteristics: 1) pin compatibility and electrical compatibility with pca82c200 independent can controller; ② SJA1000 has two working modes: basic can mode and Peli can mode. It supports can2.0a/b protocol; ③ It supports 11 bit and 29 bit ID at the same time, with bit rate up to 1m and bus arbitration function; ④ Extended receive buffer (64 bytes, FIFO), enhanced ambient temperature range (- 40 – + 125 ℃); ⑤ The ability of error detection and correction should be strengthened; ⑥ It supports live plugging.

The block diagram of SJA1000 is shown in Figure 1. The interface management logic IML is responsible for connecting the external main controller, which can be a micro controller or any other controller. The interface management logic IML receives the command from the microcontroller, allocates the control information buffer, sends the buffer TBF, receives the buffers rbf0 and rbf1, and provides the interrupt and status information for the microcontroller. The transmission buffer TBF is composed of 10 byte storage units, which are written by the microcontroller and sent to the CAN bus network. The receive buffers 0 and 1 (rbf0, rbf1) are composed of 10 bytes. They alternately store messages received from the bus. When one buffer is allocated to the CPU, the bitstream processor can write to the other. The bit stream processor is a sequence generator that controls the data flow between the transmit buffer and the receive buffer (parallel data) and the CAN bus (serial data). Bit timing logic synchronizes SJA1000 with bit stream on CAN bus. The acceptance filter supports 11 bit and 29 bit identifier filtering, and all received messages are accepted by the acceptance filter and stored in the receiving FIFO. Error management logic completes error definition according to can protocol.

  Circuit design of embedded can bus system

  can bus transceiver

PCA82C250 product of Philips company is selected as can bus transceiver. Can bus transceiver is the interface between CAN protocol controller and physical bus. The device provides differential transmission capability to bus and differential receiving capability to can controller. It has strong anti electromagnetic interference (EMI) capability and can hang at least 110 nodes.

  Can interface circuit of embedded system

Figure 2 is the can interface circuit diagram of embedded microprocessor S3C44BOX. As shown in the figure, arm and SJA1000 are connected by bus. Because arm signal is 3.3V and can bus controller level is 5V, all signals need level conversion. In this example, qs34x245 is used as level conversion chip. Qs34x245 is an 80 pin dual example in-line chip. It not only has the function of level conversion (5V to 3.3V), but also is a bus switch and isolation device. A set of 32-bit high-speed CMOS compatible bus switches are provided in qs34x245. When the oen (n is 1-4) of the output enable terminal is low level, the switch is on and connected to bus a and bus B; When the oen of the output enable terminal is at high level, the switch is off and bus a and bus B are isolated. Oe1 controls the lower 8 bits of bus a and bus B (a7-a0 and b7-b0), oe2 controls a15-a8 and b15-b8, oe3 controls a23-a16 and b23-b16, OE4 controls a31-a24 and b31-b24. Since arm bus is not multiplexed and SJA1000 bus is multiplexed, address latch signal ale must be generated by logic. In this case, the signal is generated by GAL22V10 chip. The chip selection and read-write signals of SJA1000 adopt arm bus signal, and ale signal is generated by read-write signal and address signal through gal. When writing SJA1000 register, first write data to an address of the bus. As an address, the read-write signal is invalid and the ale changes to generate a latch signal; Then write another address, read and write signal valid, as data. The above logic is completely generated by gal. In addition, the CAN bus needs to add a 120 ohm resistor between two wires.

  Circuit design of embedded can bus system

When controlling can bus, all registers are initialized first to set communication parameters (such as mode, bit rate, acceptance code, shield code, field length, bus timing, output mode, etc.). The basic can mode control section has 10 bytes in total. When sending data, first set the command register, then write the sent message to the sending buffer, and finally set the request to send, which is completed by sjal000. The receiver queries the status register, reads the receive buffer to obtain information, and then releases the receive buffer.

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