In order to realize miniaturization and low power consumption, it is a better solution to design the color timing controller as a single chip ASIC. This paper is about the ASIC design of color timing controller for HMD with LCOS (liquid crystal on silicon) micro display.
Principle of color timing
The principle of color timing method is as follows: firstly, the red, green and blue information in each field is separated, and then the red, green and blue images are written into the display screen in three subfields in each field. After the scanning process of each subfield and the liquid crystal reaction, the red, green and blue light sources are turned on in turn, so that the red, green and blue images are displayed in turn in one field, Using the characteristics of human eyes to synthesize color.
The advantage of color sequential method is that it doesn’t use color filter, one physical pixel is a real pixel, which is conducive to achieve higher resolution on the same size display screen. Compared with the method of spatial color filter, the resolution is increased by 3 times by using color sequence, that is, if the resolution is the same, the display screen size is only 1 / 3 of the original. Because the color timing divides the information of each field into three subfields and writes it into the display screen in one field, the field frequency is increased by three times, and the dot clock frequency is also increased by three times. Reducing the display area also needs to increase the frequency, which is based on the high migration performance of monocrystalline silicon. At the same time, the improvement of field frequency and point clock frequency also puts forward higher requirements for the video system design of the display.
LCOS micro display technology
LCOS micro liquid crystal display technology is a kind of micro display chip which integrates silicon-based display matrix and related driving circuits by adopting the design and manufacturing method compatible with VLSI. LCOS belongs to reflective miniature liquid crystal display technology. Its structure is to integrate the display matrix and driving circuit on the single crystal silicon substrate by CMOS process. The pixel electrode of LCOS is a reflective mirror made of aluminum, and a metal light barrier layer is set under the pixel electrode to prevent the pixel driving transistor from being exposed to strong light. The structural diagram of LCOS is shown in Figure 1. One side of the liquid crystal layer is the LCOS chip substrate with reflection electrode, the other side is ITO glass, and the thickness of the middle liquid crystal layer is generally 2 ~ 3mm.
The propagation path of light in LCOS devices is also shown in Figure 1: when the light from the light source reaches PBS (polarization beam splitter), the light from the P-pole passes through, and the S-pole is reflected to the aluminum mirror. At this time, the voltage applied between the aluminum mirror electrode and the ITO electrode will convert the S-pole into P-pole, so the light reflected by the aluminum mirror is P-pole, It can be projected to the pupil (NTE near eye display) or large screen (projection display) through PBS.
LCOS chip not only solves the connection problem between display matrix and driving circuit, but also has higher resolution, light utilization efficiency and more mature manufacturing technology compared with through LCD.
Circuit design of LCOS color timing controller
Overall structural design
The LCOS color timing controller ASIC designed in this paper can drive resolution up to 1280 × The function of LCOS micro display screen is: input 24 bit data signal (R: G: B = 8:8:8) and timing signal vs, HS, CLK, etc., write data signal R, G, B into three areas of a group of memory according to certain data transformation format, read another group of memory at the same time, and send data of R, G, B subfields into LCOS screen in order to realize color timing display. In addition, the synchronization signal and point clock signal needed by LCOS screen should be provided. In order to realize the whole process, the color timing controller must include three parts: data conversion circuit, timing signal generation circuit and storage control circuit. The overall circuit diagram is shown in Figure 2. The specific function and design of each part of the circuit will be introduced below.
Design of data conversion circuit
Because the data driving circuit of LCOS screen uses four groups of shift registers, two groups write data from the top of the screen, and the other two groups write data from the bottom of the screen, so it is necessary to write four 8-bit pixel data each time. This driving mode reduces the clock frequency of LCOS screen to 1 / 4 of that when only one group of shift registers is used for data driving. However, due to the change of writing mode, it is required to transform the original 24 bit (R: G: B = 8:8:8) data format of each pixel into four 32-bit R, G and B of each pixel, and write them into LCOS screen respectively. The idea of 8-bit shift register realizes the transformation of data from 24 bits to 32 bits.
This shift register method realizes the transformation of R, G and B from 8 bits to 32 bits. It also needs to take the data of the first, second and third group of shift registers in the first, second and third cycle of every four clock cycles, but not in the fourth cycle. In order to achieve this access mode, this paper designs a flag circuit which can generate three flag signals to control the data of three groups of shift registers.
Design of timing signal generating circuit
The main function of timing signal generation circuit is to generate some interface timing signals needed by LCOS screen, and its structure block diagram is shown in Figure 3.
Here, the clock signal is divided appropriately by two frequency dividing circuits to generate the sub field line synchronization signal s_ HS and subfield synchronization signal s_ VS； Clock masking is to generate point clock L_ Clock, so that the clock l can be stopped when no data is written_ Clock, which effectively reduces the power consumption of LCOS screen; The lighting control signal generation part obtains the lighting control signals RLED, gled and bled of three color LED light source.
Design of memory control circuit
The structure block diagram of memory control circuit is shown in Figure 4. The main function of the circuit is to generate 21 bit address signal, write control signal W and read control signal G, which can be divided into write address generator, read address generator and read write switch.
The core of the write address generator is a 21 bit counter and an adder. In the color sequential display storage, each group of memory needs to be divided into three areas to store the red, green and blue image data, and each frame of color image is decomposed into three frames for storage. In this way, the storage space required for each area is 1280 × 256 = 327680, so the write address generation circuit can actually use a 21 bit counter to generate address signals and add them to 0, 327680 and 655360 respectively. In this way, the red, green and blue images of each frame are stored within one frame.
The function of the read address generator is to generate an increasing address signal, which can be realized by the counter: the address is generated according to the line synchronization signal, and the data is read according to the field synchronization signal.
Read write switching is the key to realize real-time video display. In one frame time, the image data is output from one group of memory to LCOS display screen. At the same time, the image data is written to another group of memory through data transformation module. In the next frame time, the read write switching is carried out alternately, and continuous video data is continuously output to the display screen to realize real-time display.
Layout design of LCOS color timing controller
In this paper, the full custom design technology is adopted to design the layout of the circuit. Firstly, the standard component library is established according to 0.35mm CMOS process, and the layout is generated and post simulated by Tanner research’s l-edit. Finally, the layout of the whole LCOS color timing controller ASIC is obtained. The core of the chip is about 0.4mm in size × 5mm, and the highest working frequency can reach 100MHz.
Editor in charge: GT