With the rapid development of digital signal processing technology, digital signal processing technology has been widely used in many fields (such as communications, radar, sonar, etc.). In many cases, due to the requirement of real-time processing of signals and the increasing amount of data, a single-chip DSP chip can no longer meet the requirements. The ADSP2106X series introduced by AD Company, because of adopting the super Harvard structure, is suitable for composing various parallel multiprocessor systems, and satisfies the above-mentioned requirements well, so it is widely used at home and abroad. In the multi-chip parallel ADSP2106x processing system, the application of the link port has been paid more and more attention. In this regard, how to make full and effective use of the link port for data transmission has become a problem that the majority of DSP users must solve first.

Based on the experience of applying and debugging ADSP2106X devices in engineering, this paper focuses on discussing the applicable occasions and using methods of the link interface, and analyzes the common problems in the use process, and provides solutions.

1 Features and functions of ADSP2106X and its link ports

ADSP2106X adopts super Harvard structure, which has the characteristics of small size, high speed, large memory, flexible access, etc. It is suitable for forming various parallel multi-processor systems to complete various real-time signal processing functions, especially for radar signal processing and Sonar signal processing.

ADSP2106X provides 6 link ports, each link port includes 4-bit data lines, a bidirectional clock signal, and a bidirectional acknowledgement signal. The link handshake signals include LxCLK and LxACK, and the link port transmits 32-bit or 48-bit words in groups of four bits. The sender sends a 4-bit code on the rising edge of the clock LxCLK, and the receiver uses the falling edge of the clock to latch the 4-bit code and make LxACK valid, indicating that it is ready to receive the next word. At the beginning of each word transmission, if the sender sees that LxACK is invalid, it will make LxCLK high and wait for LxACK to be valid before sending a new word. When the transmit buffer is empty, LxCLK will remain low. If the receiving clock does not exceed the main clock (40MHz), the LCLKX2x bit of the LCOM register should be set to 0; if the receiving clock is twice the main clock, it should be set to 1. The connection relationship between the two link ports used for data communication is shown in Figure 1.

Each link port can also transmit data at twice the clock rate.

The link port has the following functions and features:

(1) Each link interface can work independently or at the same time;

(2) The link data can be packaged into 32-bit or 48-bit data, which can be accessed by the processor core, and can be transferred with the on-chip memory by DMA;

(3) External hosts can directly access the link interface;

⑷ Send and receive registers with double buffering;

⑸ It can shake hands when the link port communicates through the clock/confirmation signal, each link port can receive/transmit data, and each has a DMA channel support;

⑹ Various forms of processor networks from one-dimensional to multi-dimensional can be formed by using link connections.

There are three types of interrupts for a link port:

(1) When DMA is enabled, a maskable interrupt will be generated after DMA is completed;

(2) When DMA is disabled, the processor core can read and write the memory-mapped LBUF. When the receiving buffer is not empty or the sending buffer is not full, a maskable interrupt can be generated;

(3) When an external device accesses an unspecified link port, or accesses a link port that has been specified but the corresponding LBUF is prohibited, a maskable LSRQ interrupt will be generated.

The link port has three important registers: LAR register, LCTL register, LCOM register, they are all 32-bit registers. The LAR register (3x~3x+2 bits) represents the designated link port of LBUFx, x takes 0~5, and other bits are reserved. The LCTL register is mainly used to set each LBUF (whether to enable, whether to use DMA mode, whether to use chain DMA, send or receive data). The LCOM register contains status bits for each LBUF (empty or full), sets the rate at which each LBUF transfers data, and other functions.

ADSP2106X has 6 independent link buffers LBUF5- 0, each LBUF consists of a 2-level FIFO composed of an internal register and an external register. When LBUF is used for transmission, the internal register receives the data sent by the on-chip memory, the external register expands the data word into 4-bit codes, and the highest bit is sent first. When the data sent by the DMA or the processing core fills up the 2-level FIFO, a “full” flag will be sent. Each time a word is unrolled and sent, a position in the FIFO is vacated and a DMA request is issued. When the FIFO is empty, LxCLK is invalid. When the LBUF is used for receiving, the external register is used for data packing, and then the data is sent to the on-chip memory by DMA through the internal register. Determine the connection relationship between LBUF5~0 and LINK5~0 through the link designation register LAR. When transferring data between memories, a LINK can be assigned to two LBUFs, and DMA communication is used.

Direct data transfer (DMA) can undertake the task of data transfer without the intervention of the operation control unit, thereby improving the efficiency of program execution. ADSP2106X provides 10 DMA channels, of which only LBUF0-3 support two-dimensional DMA (that is, access a two-dimensional array element in row-major mode). The corresponding relationship between LBUF5~0 and 6 DMA channels is as follows:

DMA channel 1 link buffer LBUF0 (shared with serial port 1 receive)

DMA channel 3 link buffer LBUF1 (shared with serial port 1 transmission)

DMA channel 4 link buffer LBUF2

DMA channel 5 link buffer LBUF3

DMA channel 6 link buffer LBUF4 (shared with external port 0 EPB0)

DMA channel 7 link buffer LBUF5 (shared with external port 1 EPB1)

2-Link port settings and issues that need attention in application

For a multi-DSP system, in order to overcome the bottleneck problem of occupying the bus between the multi-processors and enhance the communication capability between the processors, the link ports of each processor are generally used for high-speed, point-to-point communication. The data connection between processors can be set as required, and the data paths of multiple link ports can work in parallel without interfering with each other. LxCLK and LxACK of each link port provide handshake signals for asynchronous data transfer between processors. Because of the use of link port communication, it allows long-distance interconnection between the sending and receiving ends. The link port adopts the self-synchronization method, so that the clock and data have only relative delay, and there is no absolute delay, which is very important for the wiring of the printed board.

If the transferred data is not a piece of data in memory, but multiple pieces of data, chained DMA can be used. First disable the LBUF to be specified by the link port, specify the LAR, set LCOM and LCTL in turn (set the LxCHEN bit to 1), and write the DMA control block to the CP register (each control block contains the information of the corresponding receive/transmit data segment). ) at the first address in memory, the chained DMA can be started; while writing 0 to the CP disables the chained DMA. After the current DMA is completed, the next set of parameters is automatically loaded by the DMA controller and placed in the (DMA) parameter register in the memory to establish the next DMA. When bit 17 of CP is 1, it indicates that an interrupt request is generated after the current DMA is completed. There are 4 DMA parameters:

IIx address (memory start address)

IMx address modifier

Cx count pointer

CPx chain pointer

Their positional relationship in memory is shown in Figure 2.

The chain DMA mode is only for the same LBUF port, and there is no chain DMA between multiple LBUFs.

If there is a single transfer of data between the two link ports, it does not matter whether the receiver DMA is set first or the sender DMA is set first; however, if the data is sent and received in multiple cycles, it must be ensured that the receiver’s DMA setting is earlier than Sender DMA, otherwise the first two 32-bit words are thrown away every time you transfer data. This is because the sender prepends two 32-bit words into the receiver’s buffer once it is ready. When the receiver sets up DMA to receive data, it first clears the cache that will be used, so the two 32-bit words are discarded. During the actual DMA transfer of data, other operations must not be performed on the LBUF being used.

When the link port is disabled, its data lines LxDAT3-0, LxCLK, LxACK are all three-state. In order to allow the sending and receiving parties to have a sequence in the time they are enabled, the LPDPD should be cleared to 0 when the link port is disabled, so that LxDAT3~0 and LxCLK and LxACK are internally pulled down (50kΩ). It should be noted that if these signal lines are left floating, internal or external pull-down resistors must be used.

The program is loaded to the DSP through the LINK port, generally using the host (host) or EPROM loading mode.

3-Link Interface Application Example Analysis

A certain type of radar signal processing system has been used in practical work. The system includes 4 arithmetic boards and a post-processing board, and the substructures of these 5 boards are exactly the same. A single DSP board includes 20 slices of ADSP2106X, processing the data of 4 channels (sum channel, auxiliary channel 1, auxiliary channel 2 and difference channel) in the same cycle at the same time, each 5 slices process one channel, and the principle of connection relationship between 4 channels basically the same. In actual work, the number of computing boards is changed according to the repetition frequency. After the computing board processes the data, it transmits the data to the post-processing board through the link interface in a time-sharing manner. Because in practice, multiple link ports will work at the same time, in order to avoid high-frequency interference between each link port when working, the requirements for the design of the printed board are very high. Due to space limitations, only the principle block diagram of the sum channel is given below, as shown in Figure 3.

LINK0 and LINK3 receive the data of the auxiliary channel respectively, LINK2 and LINK5 transmit the processed data to the post-processing board, and the 4 boards summarize the data to the post-processing board in a time-sharing manner. Through debugging, it is found that within the same computing board, when the data between each link port is transmitted at a rate of 80MHz (the operating frequency of the system clock is 40MHz), they work at the same time, and there is almost no interference with each other, which can ensure the accuracy of data transmission. It greatly improves the ability of parallel transmission. However, if data is transmitted between the 4 computing boards and the post-processing board (that is, the data is transmitted between the boards), if the rate of 80MHz is used for simultaneous transmission, the mutual interference will be relatively large, and it is difficult to ensure the correctness of the transmission; use 1x speed (40MHz) rate transmission can reduce interference, and the measures of adding filter capacitors or pull-down resistors to the handshake signal of the link port of the receiving board (ie, the post-processing board) can reduce the glitches in the signal. The system is originally designed to transmit data from the sum channel, the auxiliary channel 1 and the difference channel to the post-processing board at the same time, but in order to ensure the correctness of the data in actual work, the data of the auxiliary channel 1 is passed through the link when the requirements are met. The port is transmitted to the sum channel, and then the data is sent out by the sum channel, which reduces the number of link ports used to transmit data, and the data can be transmitted correctly. The handshake signal line between the link ports is connected by cable (usually twisted pair). At present, this system has been well applied in a certain type of radar.

Engineering practice shows that the full use of the link port in the parallel multi-DSP system can ensure the reliability of data transmission, overcome the bottleneck problem of occupying the bus between multiple processors, and enhance the communication ability between processors.

Responsible editor: gt

Leave a Reply

Your email address will not be published.