Have you checked how many items about “ADC buffer design” are on the network? The answer is more than 4million, and it is difficult to find the content we need in so many references. For most analog and mixed signal data acquisition system design engineers, this may not be very unexpected, because designing the external front end of unbuffered analog-to-digital converter (ADC) requires patience and a lot of advice. It is often regarded as an art form and a reserve for eccentric masters who have mastered its tricks after years of exploration. For inexperienced people, this is a frustrating trial and error process. Most of the time, because there are many interrelated specifications, designers have to make many tradeoffs (and evaluations) to achieve the best results.

1 challenge

The design of amplifier stage consists of two different stages related to each other, so the problem becomes difficult to model mathematically, especially because there are nonlinear factors related to these two stages. The first step is to select an amplifier to buffer the sensor output and drive the ADC input. The second step is to design a low-pass filter to reduce the input bandwidth, so as to minimize out of band noise.

The ideal amplifier is to provide just a good bandwidth to properly buffer the signal generated by the sensor or transmitter without adding additional noise, and the power consumption is zero, but the actual amplifier is far from this. In most cases, the amplifier specification will determine the overall system performance, especially in terms of noise, distortion and power consumption. In order to better understand the problem, the first step is to understand the working principle of discrete-time ADC.

Discrete time ADC obtains samples of continuous time analog signals, and then converts them into digital codes. When the signal is sampled, there are two different cases of the same inherent problem according to the type of analog converter.

Saradc integrates a sample holder, which is basically composed of a switch and a capacitor. Its function is to hold the analog signal until the conversion is completed, as shown in Figure 1.

Discrete time Sigma – ∆ ADC or oversampling converter realizes a similar input stage, that is, an input switch with a certain internal capacitance. The sampling mechanism of Sigma – ∆ ADC is slightly different, but the sampling input architecture is similar, using switches and capacitors to maintain a copy of the analog input signal.

In both cases, the switch is realized by CMOS process, and the resistance when closing is non-zero, usually a few ohms. The combination of this series resistance and sampling capacitance (PF level) means that the ADC input bandwidth is often very large, which is much larger than the ADC sampling frequency in many cases.

2. Bandwidth problem

For the converter, the input signal bandwidth is a problem. In the sampling theory, we know that frequency signals higher than the Nyquist frequency (half of the ADC sampling frequency) should be removed, otherwise these frequency signals will produce mirroring or aliasing in the target frequency band. Generally, a considerable part of the power in the noise spectrum exists in the frequency band above the Nyquist frequency of ADC. If this kind of noise is not treated, it will mix below the Nyquist frequency, increase the background noise (as shown in Figure 2), and significantly reduce the dynamic range of the system.

ADC input signal bandwidth and buffer output bandwidth are the first problems to be solved. In order to ensure that the noise will not be aliased downward, the bandwidth of the ADC input signal must be limited. This is not a small problem.

Generally, the selection of amplifier is based on the specification of large signal bandwidth (i.e. swing rate) and gain bandwidth product, so as to cope with the extreme situation of input signal, which determines the fastest changing signal that ADC can track.

However, the effective noise bandwidth of the amplifier is equal to the small signal bandwidth (usually considered for signals less than 10mvp-p), which is often at least four to five times higher than the large signal bandwidth.

In other words, if the large signal specification is selected for 500KHz, the small signal bandwidth can easily reach 2MHz or 3MHz, which may cause ADC to collect a lot of noise. Therefore, before inputting the analog signal into ADC, the small signal bandwidth should be limited externally, otherwise the measured noise will be three to four times the ADC Data Book specification. Table 1. Noise converted from amplifier to output, RTO

Remember that the thermal noise produced by the amplifier depends on the amplifier gain and the total system bandwidth. The circuit example is shown in Figure 3, and the noise source is summarized in Table 1, where:

T is the temperature (in K),

K is Boltzmann constant (1.38 × 1023 J/K），

The unit of resistance is Ω,

BW refers to the small signal bandwidth.

The above formula shows that it is important to add a low-pass filter with sufficient attenuation performance before the ADC input pin to minimize the sampling noise, because the noise is proportional to the square root of the bandwidth. Usually, using discrete resistors and capacitors to realize a first-order low-pass filter with a sufficiently low cut-off frequency can eliminate most of the broadband noise. An additional advantage of the first-order low-pass filter is to reduce the amplitude of any other large signals outside the target frequency band and prevent them from being sampled by ADC and possible aliasing.

But it’s not over yet. ADC internal switching resistance and capacitance define the analog input bandwidth, but due to the change of input signal, time-domain charge discharge cycle will occur. Each time the switch (the external circuit connected to the sampling ADC capacitor) is closed, the internal capacitor voltage may be different from the voltage previously stored on the sampling capacitor.

3 what is the problem of backlash?

The following is a classic simulation problem: “if there are two shunt capacitors connected to a switch, and when the switch is disconnected, one capacitor stores some energy, what will happen to the two capacitors when the switch is closed?”

The answer depends on the ratio between the energy stored by the charging capacitor and the capacitance. For example, if two capacitors have the same value, the energy will be divided equally between them, and the voltage measured between the capacitor terminals will be halved, as shown in Figure 4.

This is the problem of backlash. Some ADCs perform internal calibration to compensate for internal errors, which is called self stabilizing zero calibration. These procedures will make the sampling capacitor voltage close to the supply rail or another voltage, such as half of the reference voltage.

This means that the external signal buffered by the amplifier and the sampling capacitance (which must save the analog value in order to obtain a new sample) are often not at the same potential (voltage). Therefore, the sampling capacitor must be charged or discharged to have the same potential as the buffer output. The energy required for this process will come from the external capacitance (the capacitance in the low-pass RC filter) and the external buffer. This charge redistribution and voltage establishment will take some time, during which the voltage at each point in the circuit will be disturbed, as shown in Figure 1. The amount of charge redistributed may be large, equivalent to current flowing into or out of the amplifier and into the capacitor.

As a result, the amplifier should be able to charge / discharge the external capacitance of the low-pass filter and the sampling capacitance of the ADC in a very limited time, and the low-pass filter resistor will be used as a current limiter.

More specifically, the amplifier should be able to charge / discharge the capacitor from the sampling capacitor and an external source within a given error range. The cut-off frequency of the external low-pass filter should be slightly higher than the target frequency band, which is defined by the time constant of the filter, the number of bits of ADC and the worst-case conversion between samples (that is, the worst-case input step that we should be able to accurately measure).

4 how to solve the problem of backlash?

A simple way to solve this problem is to choose an amplifier with sufficient voltage swing rate, bandwidth gain product, open-loop gain and CMRR, and place the maximum capacitance you can find in the market on the output end, and the resistance is small enough to meet the bandwidth requirements of low-pass filter.

Because the capacitance is very large, the recoil problem will be negligible, and the bandwidth is limited by the low-pass filter, so the problem can be solved, right?

Unfortunately, the above solution will not work, but if you are curious and want to try the above solution, you will find two points: the capacitance will be as large as the condensed milk container, and the amplifier does not like the virtual impedance at the output end.

The performance of the amplifier depends on the imaginary impedance seen by the amplifier. In this case, the disadvantage of low-pass filter is the performance degradation of thd and setup time. The increase of setup time will cause the amplifier to fail to charge the capacitor, making the voltage sampled by ADC not the correct final voltage. This will aggravate the nonlinearity of ADC output.

In order to better illustrate the above point, figure 5 shows the performance difference of the amplifier driving different resistive loads. Figure 6 shows the small signal overshoot caused by capacitive load, which will affect the establishment time and linearity.

In order to solve this problem to the greatest extent, the output of the amplifier should be isolated from the external capacitance through the series resistance of the low-pass filter. The resistance should be large enough to ensure that the buffer will not see the imaginary impedance, but small enough to meet the required input system bandwidth and minimize the IR voltage drop caused by the current flowing from the buffer on the resistance (the amplifier may not be able to stabilize this voltage drop fast enough). At the same time, the resistance should support the external capacitance to be reduced to a small enough value to minimize the recoil without affecting the setup time.

Fortunately, there are some tools that allow us to predict the combined performance of ADC, amplifier and filter, such as precision ADC driver tool. This tool can simulate the performance of recoil, noise and distortion, as shown in Figure 7.

5 rule of thumb for low pass filters

Generally, first-order low-pass filters appear in many suggestions, but why does no one use higher-order filters? Unless the application clearly requires the elimination of large out of band interference or harmonics in the input signal, increasing the order of the filter will bring additional complexity to the system. Generally speaking, the compromise solution is to make the small signal bandwidth slightly higher than the demand, which will affect the noise, but the advantage is that it can easily drive the ADC input stage and reduce power consumption and cost.

6 reduce the burden

As we mentioned earlier, amplifiers don’t like virtual impedance and / or provide large current, but this is inevitable because virtual impedance is brought by capacitance, which can solve the problem of backlash.

The only way to improve this situation is to reduce backlash. This solution has been adopted by the latest ADI converters, such as ad7768 and ad4000.

Due to different converter architectures, each device adopts different solutions. The ad4000saradc can operate at a power supply lower than the analog input range. The solution adopted is called high resistance mode, which is only applicable to sampling frequencies below 100kHz.

In ad7768, the power supply is equal to or higher than the analog input range. The solution adopted by ad7768 is called precharge buffer. Contrary to high resistance mode, its working frequency can reach the maximum sampling frequency of ADC.

Both solutions are based on the same working principle. The main difficulty of driving ADC is capacitor charge redistribution. In other words, when the internal switch reconnects the sampling capacitor, the lower the voltage drop seen by the input buffer and low-pass filter, the smaller the voltage backlash, and the ADC input current decreases accordingly. Therefore, the easier it is to drive the ADC and the shorter the setup time. The voltage drop on the filter resistance is reduced, so the AC performance is improved.

Figure 8 shows the effect of precharge buffer and high resistance mode enable and disable on input current.

The higher the input current, the higher the bandwidth of the amplifier (i.e., the faster). Therefore, the input low-pass filter bandwidth should be higher, which will affect the noise.

For example, for 1kHz input signals sampled with 1msps, SINAD is used to evaluate performance. Under different filter cut-off frequencies, we get the results shown in Figure 9.

The figure above shows that compared with the same configuration but the high resistance mode is off, the low input current (the high resistance mode is on) reduces the filter cut-off frequency requirements and the IR voltage drop of the filter resistance, and improves the ADC performance.

It can be observed from Figure 9 that by increasing the cut-off frequency of the input filter, the external amplifier can charge / discharge the sampling capacitor faster, but at the cost of increased noise. For example, when the high impedance mode is turned on, the sampling noise at 500KHz is less than that at 1.3mhz. Therefore, SINAD is better at 500KHz input bandwidth. In addition, the capacitance required by the low-pass filter will be reduced, which will help to improve the performance of the amplifier driver.

The features implemented in ADI’s latest ADC, which are easier to drive or reduce the burden, have some significant effects on the whole signal chain. The key advantage of ADC designers introducing some driving problems into ADC chip itself is that the solution can be designed to meet the signal requirements of ADC as efficiently as possible, so as to solve some problems, including input bandwidth and amplifier stability.

Reducing the current flowing into the ADC input, thereby reducing the backlash, means that the voltage step to be processed by the amplifier is low, but it still has the same full sampling period as the standard switched capacitor input.

Reducing the step voltage to be established within a given time has the same meaning as using a longer time to establish a larger step. The net effect is that the amplifier now does not need such a wide bandwidth to fully establish the input to the same final value. Reduced bandwidth usually means lower power consumption of the amplifier.

There is another way to look at this situation: imagine that an amplifier that is usually considered to have insufficient bandwidth to establish a given ADC input can now be fully established with a pre charged buffer enabled.

ADI application note an-1384 introduces the performance of a series of amplifiers when used with ad7768 in three power consumption modes. One of the amplifiers introduced in this document is the ada4500-2. When the pre charge buffer is not used, it is difficult to establish the input of the ad7768 (THD ± -96db) in the medium power mode. However, when the precharge buffer is enabled, the performance is significantly improved to better than -110dbthd.

Ada4500-2 is a 10MHz bandwidth amplifier. The bandwidth required for the establishment of ad7768 in a given mode is about 12Mhz. We can see that the easy drive feature now supports the use of this lower bandwidth amplifier. Therefore, these characteristics not only make the design of front-end buffer circuit easier, but also allow more freedom to select components to maintain within the power consumption or thermal limits of the system.

The second advantage of the reduced current flowing into the ADC analog input pin is that the current flowing through the series resistor, which is used as part of the input RC network, is now reduced.

For traditional ADC input, relatively large current means that only a small value resistor can be used, otherwise a large voltage drop will be generated on the resistor. The large voltage drop here may lead to gain error or linear error in ADC conversion results.

However, using smaller resistance values also presents challenges. Using smaller resistors to achieve the same RC bandwidth means using larger capacitors. However, this combination of large capacitance and small resistance may cause instability of the buffer amplifier.

The current reduction encountered when using the easy drive feature means that a larger value of resistance can be used without affecting the performance and ensuring the stability of the system.

Considering the circuit design advantages described above, it is obvious that using these features can also obtain performance advantages or opportunities to further improve performance.

The advantage that has been mentioned is that it can use the lower bandwidth amplifier to achieve better performance, but also can be used to expand the performance of a more optimized system. For example, even for input signals that have been fully established, when the final establishment occurs, there may still be some mismatches between the inputs. Therefore, features such as enabling the precharge buffer will mean that the final establishment will be much smaller, so the highest level of thd can be achieved, which was previously impossible.

The reduction of the current flowing through the series resistance of the RC network is also conducive to performance. In addition, not only does the input current decrease significantly, but it is almost independent of the input voltage. Thd can also be improved, because any mismatch between the input and the upper resistance will cause a small voltage difference at the ADC input, and the voltage drop is not signal dependent.

Low input current also affects the offset and gain accuracy. Due to the decrease of absolute current and the decrease of signal related current change, the possibility of large changes in offset and gain error caused by the change of component value on each channel or each circuit board is also small (similarly, lower current leads to smaller voltage on the series resistance). Better absolute offset and gain error specifications can be achieved by using the precharge buffer, and the performance of different circuit boards or channels in the system will be more consistent.

In systems where ADC sampling rates vary to meet different signal acquisition requirements, such as in data acquisition cards, lower current has another advantage. Without a precharge buffer, the voltage drop on the input passive component changes with the sampling rate of the ADC, because at higher sampling rates, the ADC input capacitors often charge and discharge more frequently. This applies to both the analog input path and the reference input path. ADC regards this voltage change as the offset and gain error related to the sampling rate.

However, when the pre charging buffer is enabled, the absolute current and the corresponding absolute voltage drop will be much smaller at the beginning, so the voltage change caused by the change of ADC sampling rate will be much lower. In the final system, this means that it is not necessary to recalibrate the system offset and gain error when adjusting the sampling rate, and the offset and gain error are not so sensitive to the change of ADC sampling rate.

One of the main advantages of easy-to-use features relates to the total cost. The design and performance advantages in all aspects may reduce the development cost and operation cost.

Simpler design means less design work and faster time to complete the first prototype.

The probability of a successful prototype design is greater.

The easy drive feature supports lower bandwidth, so lower cost amplifiers can be used.

Offset and gain advantages can reduce factory calibration.

Performance improvements can reduce on-site calibration or on-demand calibration, thereby reducing downtime and / or increasing production. 