For FPGA learners, how to learn FPGA is a constant debate. Some people think that we should learn the HDL hardware description language first; Some people say that they have to learn digital and analog electronics first. Without this knowledge, even if they have learned the language, they will have a very difficult time in the future. But the only thing we all agree is to master the basic structure of FPGA.
Let’s take a look at the family tree of FPGA first. The development of electronic technology, such as electron tubes, transistors and integrated circuits, will not be mentioned. Starting from ASIC (application specific integrated circuit), it reduces the cost of products, reduces the physical size of the design, and increases the stability of the system (low, small and stable). However, it also has some limitations, such as long design cycle, poor flexibility, and large investment (expensive, complicated, and long time) in revision. People hope to have a more flexible design method, in the laboratory can design, change large-scale digital logic, develop their own ASIC, and immediately put into use, so there is the basic idea of programmable logic.
1、 Programmable logic device
Programmable logic device (PLD) is a kind of digital integrated circuit which can change and configure the internal connection structure and logic unit of the device by means of software.
Programmable logic devices can be divided into: PAL / gal, CPLD, FPGA.
PAL / gal: (programmable array logic) programmable array logic, (Generic Array Logic) general programmable array logic. Most of them are based on e ^ 2cmos technology, with simple structure and low logic cell density, which can only be applied to some simple digital logic circuits.
CPLD: (complex programmable array logic) complex programmable array logic. It is developed on the basis of PAL / gal, most of which adopt e ^ 2coms process, and a few adopt flash process. Of course, its logic function has been greatly improved, and it can complete the higher speed and more complex logic functions in logic design.
FPGA: (field programmable gate array) field programmable logic array. It is developed on the basis of CPLD, generally using SRAM process, some also using flash process or anti fuse process. It is highly integrated. It can complete extremely complex sequential and combinational logic circuit functions, and is suitable for high-speed and high-density high-end digital logic circuit design.
2、 The basic structure of FPGA
The simplified FPGA consists of six parts: programmable I / O unit, basic programmable logic unit, embedded block ram, rich wiring resources, underlying embedded function unit and embedded special hard core. The following are to explain these parts.
1. Programmable I / O unit: referred to as I / O unit, is the interface part between the chip and the external circuit, which is used to drive and match the input / output signals under different electrical characteristics. At present, most FPGA I / O units are designed in programmable mode, which can adapt to different electrical standards and I / O physical characteristics through software configuration; The matching impedance characteristics can be adjusted, and the pull-down resistance can be adjusted; The output driving current can be adjusted.
It doesn’t matter if you can’t understand some of the above concepts now. With the deepening of learning, if you look back, you will deepen your understanding. Now we only need to know the flexibility of FPGA, one of which is reflected in the I / O interface, because it can be configured by software programming.
2. Basic programmable logic unit: it is the main body of programmable logic, and can flexibly change its internal connection and configuration according to the design to complete different logic functions. The basic programmable logic unit of FPGA is almost composed of LUT and reg. FPGA generally relies on the look-up table to complete the combinational logic function, and relies on the register to complete the synchronous sequential logic design. Altera programmable logic unit is usually called Le (logic element), which is composed of 1 LUT + 1 reg. Several Les are organically combined to form a larger functional unit, logic array bolck (logic array bolck). In addition to le, lab also includes carry chain between les, lab control signal, local interconnect resources, LUT cascade chain, register cascade chain and other connection and control resources. The programmable logic unit of Xilinx is called slice, which is called LC (logic cell). The bottom logic unit of lattice is called PFU (programmable function unit).
You only need to know that FPGA is based on LUT and registers. Of course, you may have known this before, but I believe your understanding after reading it is different from before.
3. Embedded block ram: programmable RAM module is embedded in FPGA, which greatly expands the application scope and flexibility of FPGA. The common storage structures, such as single port RAM, dual port RAM, cam and FIFO, must be familiar to all of us. There is no ROM resource in FPGA, and the essence of ROM implementation is ram.
4. Abundant wiring resources: the wiring resources connect all the internal units of FPGA, and the length and technology of the wiring determine the driving ability and transmission speed of the signal on the wiring.
a. Global dedicated wiring resources: used to complete the wiring of global clock and global reset / set in the device.
b. Long line resource: complete the wiring of some high-speed signals and some second global clock signals between devices (partitions).
c. Short line resources: complete the logic interconnection and wiring between basic logic units.
In addition, there are various wiring resources and special clock, reset and other control signal lines.
5. Bottom layer embedded functional unit: the concept of bottom layer embedded functional unit is more general, which refers to those embedded functional modules, PLL, DSP, CPU, etc. With the development of FPGA, these modules are more and more embedded in FPGA to meet the needs of different occasions.
6. Embedded dedicated hard core: the hard core here mainly refers to those with weak universality, not all FPGA devices contain hard core. FPGA and CPLD are general logic devices, which are relative to ASIC. There are also two camps in FPGA: on the one hand, FPGA with strong versatility, wide target market and moderate price; On the one hand, it is FPGA with strong pertinence, clear target market and high price.