Among all kinds of PLL structures, charge pump PLL is widely used in wireless communication, frequency synthesizer and clock recovery circuit because of its high stability, large acquisition range and easy integration. With the integration of chip design and the simplification of circuit design, PLL chips are usually integrated with loop lock detection circuit.
The lock detection circuit design of charge pump PLL includes analog lock detection and digital lock detection. Among them, the analog detection circuit uses the phase error output by PFD to generate pulse signal to charge and discharge the external capacitor. It takes a long time to achieve a stable level output to indicate whether the current PLL state is locked or out of lock. The circuit design is not flexible enough and lacks accurate judgment of the locking state of PLL, which limits its application scope. Digital lock-in detection method is widely used because of its high accuracy, programmability and easy circuit design. At present, in the design of digital lock indication circuit of charge pump phase-locked loop, it is usually realized by detecting the phase error of reference clock input after frequency division and local oscillator feedback signal after frequency division in PFD circuit. When the phase error exceeds a lock detection window, the phase-locked loop circuit will report the loss of lock indication signal. This paper introduces the basic principle of lock-in detection of charge pump phase-locked loop circuit. By analyzing the key factors that affect the digital lock-in circuit of phase-locked loop, the calculation formula of phase error is derived. Taking cdce72010 as an example, it is verified by experiments that how unreasonable circuit design or peripheral circuit parameters affect the accuracy of digital lock indication of charge pump PLL chip.
The principle of digital lock detection for 2 charge pump PLL
Phase error is the key parameter of digital lock-in detection principle. This paper analyzes the source of phase error in charge pump phase-locked loop circuit and how the digital lock-in detection circuit is realized based on phase error.
2.1 PFD, charge pump current and phase error
The PFD working principle of a typical charge pump PLL circuit (such as TI’s cdce72010) is shown in Figure 1. When delivered to PFD reference
When the clock input is ahead of the local oscillator clock input, PFD1 will input a high pulse width signal; otherwise, PFD2 will output a high pulse level width, through the pulse signals of PFD1 and PFD2 to control the charge pump current input and output, after the low-pass filter, different voltage control voltage will be generated to control the output of the external oscillator, so as to achieve negative feedback stability. Usually, PFD circuit compares the time delay between the rising edge of reference clock and local oscillator clock, which is called phase error. When the circuit is locked, the phase error is the steady-state phase difference parameter of PLL.
2.2 digital lock detection principle
The basic principle of digital lock detection is to compare the phase error with the preset lock detection window tlock_ Once the phase error falls within the preset detection window in N consecutive cycles, the digital detection circuit indicates that the PLL is in the locked state; while in the locked state, once the phase error exceeds the set detection window, the digital detection circuit indicates that the PLL is in the unlocked state.
Figure 3 is the schematic diagram of the digital lock detection circuit of cdce72010 device. When cdce72010 is in the lock state, the lock indication signal PLL_ Lock output output is high. Among them, the value of N can be 1, 16, 64 or 256, and the lock detection window has a wide range from 1.5ns to 28.6ns (at room temperature), which can meet the needs of most applications.
Design of digital lock circuit
Because the digital lock detection circuit judges the lock indication by analyzing whether the phase error of PLL falls within the preset lock detection window, and the application scene of PLL is complex, the circuit design in practical application is quite different, the phase error parameters are greatly affected by the PLL circuit design, and the improper circuit design and peripheral device selection may have a great impact The phase error exceeds the maximum lock detection window of PLL chip. Therefore, it is necessary to select the appropriate detection window according to the specific PLL configuration and peripheral circuit, or design the appropriate PLL parameters and peripheral circuit according to the requirements of the detection window. This section analyzes the key parameters that affect the timing phase error of PLL lock, and focuses on how to design the digital lock indication circuit reliably.
3.1 phase error analysis of charge pump phase locked loop
Figure 4 is the leakage current model of charge pump PLL circuit based on cdce72010, including passive filter circuit and local voltage controlled oscillator VCO or VCXO. Ideally, the phase error of PLL circuit should be 0, but due to the non ideal characteristics of components, there are the following leakage currents: charge pump leakage current I1, leakage current I2 introduced by capacitors C1, C2 and C3 of filter circuit and leakage current I3 introduced by local voltage controlled oscillator. These leakage currents (I1 + I2 + I3) will affect the phase error of PLL in locked state.
When the phase-locked loop is in the locked state, if the phase error is Δ T, the pulse width of the charge pump is Δ T, and the amplitude of the current is ICP, then the amount of charge accumulated on the low-pass filter capacitor in a phase discrimination period T is Q1 = Δ t · ICP. At the same time, the leakage charge of the PLL circuit is Q2 = t · (I1 + I2 + I3) in a phase discrimination period. If the voltage control voltage in the locked state remains stable, the charge Q1 supplemented by the charge pump should be equal to the charge Q2 leaked by the leakage current
Among them,It is the phase frequency of PLL circuit.
Figure 4 leakage current model of phase error in cdce72010 circuit
In the leakage current model shown in Figure 4, I1 is introduced by PLL chip. The charge pump leakage current index of cdce72010 is less than 100na. At present, the leakage current I2 of ordinary ceramic capacitor is far less than 100na, while the leakage current I3 of VCO can be equivalent to the current flowing through the input impedance of VCO. The index of oscillators of different specifications is quite different, usually reaching UA Level. Therefore, the equivalent input impedance of VCO is the key source of phase error in PLL.
The VCO / VCXO with 3.3V supply voltage is usually used in the phase-locked loop circuit with cdce72010. The Vctrl of Vctrl is generally stable at about 1.65v. According to equation (1), if the leakage current of I1 and I2 is ignored, the phase error introduced by the input impedance of VCO / VCXO in the locked state is as follows:
According to equation (2), in order to reduce the phase error during locking, the phase detection frequency f PFD, charge pump current IP and input impedance RI of VCO can be increased as much as possible.
3.2 digital lock detection circuit design and experimental test
In the design of digital lock detection circuit, it must be strictly ensured that the phase error Δ t is less than the lock detection window tlock_ Window，
Otherwise, the digital lock indication signal will be misjudged. According to the previous analysis, in the cdce72010 PLL circuit, the input impedance of external VCXO is a key parameter in the design of digital locking circuit
Assuming that the phase discrimination frequency of cdce72010 is 1MHz, the charge pump current is 1, the preset lock detection window is 5.8ns, and the voltage control voltage of local VCXO is 1.65v, the input impedance requirements of VCXO can be obtained
In the design of PLL circuit, the phase detection frequency and charge pump current are directly proportional to the DC gain of the loop, which is closely related to the loop bandwidth and phase margin of the PLL. In order to get a smaller loop bandwidth, it is usually necessary to reduce the phase detection frequency or charge pump current. Further analysis of equation (2) shows that the phase error is inversely proportional to the phase discrimination frequency and charge pump current. Therefore, in the design of low loop bandwidth circuit, special attention must be paid to the input impedance (or leakage current index) of VCO and the design of lock-in detection window to strictly meet the design requirements of equation (3).
The correctness of equation (3) can be checked by experiments. On the evaluation board of cdce72010, the equivalent input impedance of VCXO voltage control terminal is changed. By observing the locking state of cdce72010 lock indication output pin or lock indication register, the reliability of the lock detection circuit is analyzed
The reference clock is 25MHz, the VCXO frequency is 125MHz, the phase discrimination frequency is 1MHz, the detection window of PFD is 5.8ns, and the control voltage is 1.65v. The experimental results are shown in Table 1, where ri_ Min is the minimum value of VCXO input impedance calculated, √ indicates that the PLL indicates locking, and X indicates that the digital locking indication of the PLL is out of lock. During the experiment, the reference clock and lo clock of cdce72010 monitored by oscilloscope are always locked.
Table 1 Influence of different VCXO input impedance values on digital locking indication of cdce72010
It can be seen from table 1 that the input impedance of VCXO has a great influence on the digital locking of PLL. For example, when the charge pump current is 1.2mA, the minimum input impedance of VCXO can be 237kohms according to equation (3). For the input impedance lower than this value, the digital PLL indication cannot correctly indicate the locking. The experimental results are consistent with the theoretical analysis.
Based on the principle of digital lock-in detection of charge pump phase-locked loop, this paper analyzes the loop parameters and the key parameters of peripheral components, including charge pump current, phase detection frequency and leakage current. At the same time, according to the analysis of the leakage current path of the whole loop, the influence of the equivalent input impedance of the external VCO on the locking indication accuracy of the PLL is analyzed.
Taking the design of cdce72010 digital lock-in circuit as an example, in order to improve the accuracy of lock-in state indication of digital lock-in detection circuit, the appropriate input impedance parameters of external VCO must be selected in the design of low loop bandwidth PLL circuit.
Editor in charge: GT