Therefore, it is particularly suitable for high gain and high precision signal conditioning circuit. For example, sensors (such as temperature, pressure or load cells) generally produce low-level output voltage, so an amplifier is needed to amplify the signal without introducing more errors. Zero drift amplifier is designed for ultra-low offset voltage and drift, high common mode rejection, high power supply rejection and lower 1 / f noise. It is an ideal choice to achieve high resolution in high demand system applications (such as detection applications) and has a long product life cycle.

Basic architecture of zero drift amplifier

Figure 1 shows the circuit diagram of the basic chopper amplifier (unity gain configuration). The DC gain path includes input chopper switching network (chop in), first transconductance amplifier (GM1), output chopper switching network (chop out), second transconductance amplifier (GM2) and frequency compensation capacitors (C1 and C2). Chop and chop are controlled by clock generator and function to correct undesired AMPLIFIER DC offset voltage (VOS).

Figure 2 shows the related sequence diagram and the expected output voltage (VOUT). When the chop clock signal is high level (stage a), the differential input and output of the amplifier GM1 are connected to the signal path without inversion. Due to the presence of Vos, a positive output voltage Vout is generated. When the chop clock signal is high level (B stage), the input and output of GM1 are connected to the signal path and reversed, and a negative output voltage is generated due to Vos. The positive and negative output voltage from GM1 makes the output voltage equal to ± Vos. This chopping concept in time domain is similar to modulation in frequency domain. In other words, GM1 offset voltage is modulated upward from chopout to chopper frequency. On the other hand, the input signal is chopped twice by chop in and chop out. This is equivalent to an input signal modulated up and then down to the original frequency. Therefore, the input signal entering the output does not reverse.

The positive and negative output voltage (± Vos from GM1) appears in the form of voltage ripple in Vout (Fig. 2). In addition, chop and chop clocks are coupled to the differential input pins via switch related parasitic capacitance. After the clock changes state, charge is injected into the differential input pin. These injected charges are converted into output voltage via limited input source impedance. The magnitude and shape of the burr depend on the impedance of the input source and the amount and matching degree of the charge injected into the differential input pin. The output ripple and burr will produce switching artifacts, and increase at the chopping frequency and its integer multiple frequency in the noise spectrum. In addition, the switching artifact amplitude and frequency of each zero drift amplifier are different, and the components are also different. In this paper, the terms “chopper” and “switching frequency” are used interchangeably.

Figure 1. Chopper architecture

Figure 2. Chopping sequence diagram

Switching artifacts in Data Book

Generally speaking, the zero drift amplifier has a large broadband noise and low switching frequency, ranging from several thousand Hz to tens of kHz. This limits them to DC and below 100 Hz applications to keep the switching frequency out of the target signal bandwidth. For applications requiring high accuracy and low drift in higher bandwidth, it is important to use zero drift amplifier with higher switching frequency. In fact, the switching frequency can sometimes be regarded as the quality factor of the zero drift amplifier. The new zero drift amplifier adopts advanced design architecture and is designed for low switching artifacts at much higher frequencies. For example, in addition to chopping the offset voltage at 4.8 MHz, the high voltage, dual channel, zero drift amplifier ada4522-2 also uses patented offset and ripple correction loops to minimize switching artifacts. The working frequency of the calibration loop is 800 kHz, which is used to eliminate the offset voltage ± Vos (as shown in Figure 2). Reducing ± Vos to 1% of its initial value can improve 40 dB switching artifacts. This can reduce the workload of system designers to achieve the system level accuracy target.

The simplest way to detect switching artifacts is to observe the voltage noise density spectrum of the amplifier. Figure 3 shows the voltage noise density map of ada4522-2 converted to input. Note that channel B exhibits an increase in the noise spectrum at its 800 kHz switching frequency. As mentioned above, the increase of noise spectrum is a side effect of charge injection mismatch. Because mismatch depends on device to device and channel to channel, the amplitude of noise spike is different, and not all devices will show noise spike. For example, channel a of the same device does not show any noise spike at 800 kHz switching frequency. The switching frequency of each device can vary from 10% to 20%, depending on the frequency of the on-chip clock oscillator.

Figure 3. Voltage noise density of ada4522-2

Noise comparison between different zero drift amplifiers

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