In this article, we will continue to discuss the advanced learning path of FPGA. Different from the entry route, I want to analyze what technical capabilities professional FPGA developers need to have and how to further improve their capabilities from the perspective of career development. So if you are interested in the FPGA industry, or are looking for work in this field, or have been in the industry for some time, and hope to clarify the development direction in the future this year, then this article should be helpful to you.
Compared with beginners, professional FPGA engineers need to master more skills and knowledge. In this regard, I summed up four aspects, namely, FPGA related advanced skills, domain related knowledge, and professional chip engineers must have the hard power and soft power. I will also introduce some books and learning materials, hoping to be helpful to your study.
Advanced development skills of RTL design
After mastering the basic knowledge, we need to continue to learn some advanced skills related to FPGA and digital circuit design. There are many contents in this part, mainly including design, verification, and some FPGA constraints and optimization techniques and methods.
The design here refers to the logic design, that is, the use of RTL language to achieve some relatively complex modules or systems, as well as some skills used in the implementation process. In this paper, we will not discuss the content of high-level synthesis (HLS), that is, to use C language or Python and other high-level languages to program FPGA. For the related content of HLS, please refer to my previous article “high level synthesis: the last jigsaw puzzle to unlock the wide application of FPGA”.
For RTL design, a very common problem in the interview is the signal cross clock domain processing. For example, when crossing the clock domain, how to deal with one bit signal, how to deal with multi bit irrelevant signal, how to deal with multi bit bus signal, how to deal with reset, how to deal with pulse, how to do from fast clock domain to slow clock domain, and vice versa. The synthesizer of this kind of problems is the design of FIFO, especially the design of asynchronous FIFO, and a series of its variants.
Architecture block diagram of asynchronous FIFO
On the issue of cross clock domain and FIFO, I recommend readers to carefully study Clifford Cummings’ several articles. His articles discuss all the above issues in a very comprehensive way, and I will share his representative works in the knowledge planet.
In fact, Cummings, as a participant in protocol making of Verilog language, has also written many articles to discuss various issues related to digital circuits in detail, such as how to write good comprehensive RTL code, how to write state machine, UVM and verification, and many details of system Verilog and Verilog.
For advanced friends, I think this book also has some reference value. It’s called FPGA design practice – advanced skills. It introduces some common FPGA design techniques and methods, such as the clock domain processing mentioned above, and how to exchange and optimize the speed and area, etc.
It’s worth noting that although cross clock domain processing is often asked in the interview, it’s basically impossible for you to write a cross clock processing module or FIFO from the beginning in the actual project. These functions have long been packaged into ready-made modules, which can be called directly.
But this is not the so-called “interview makes rocket, work screw”. The advanced skills mentioned above are more to exercise our way of thinking and design habits. Only by knowing these, can we know how to analyze, design and implement according to the requirements and get the optimal results when facing a practical problem.
Advanced techniques of verification
Let’s talk about verification. As mentioned in previous articles, validation is a very complex area. For example, the following image of mentor shows that in a chip project, on average, at least half of the time is spent on verification, and some even account for 60% – 70%. In my own experience, the proportion will be higher.
Verification is complex and time-consuming because we have to check all possible design functions and states as much as possible. There is a concept of “functional coverage” in verification, which is used to quantify the process. For example, for an adder circuit, a + B = C, we certainly want to verify that when a and B take all values, the value of C is correct. If a and B are both decimal numbers, that is, randomly selected from 0 to 9, then there are 10×10 = 100 possibilities. But if a and B are both four decimal numbers, there are 10000 x 10000 = 100 million possibilities. Of course, this is a very simple case.
For more complex designs, such as the addition and multiplication of multiple numbers, or logic functions in some specific fields, such as AI or network applications, it is difficult for us to verify all possible states through simulation, or even cover all possible design states.
In order to solve this problem, we need to make a scientific verification plan, and use some advanced verification methodology, such as random constraints, UVM or formal methods commonly used in the industry, to help us build a more efficient verification environment.
Schematic diagram of a basic UVM verification environment
Many chip companies actually have a division of labor between design engineers and verification engineers, but this does not mean that chip designers do not need to know verification. As a matter of fact, those excellent chip designers are also excellent verifiers. They may not use UVM or formal verification methods, but they will certainly be proficient in random constraints, reference model modeling, automated testing, assertions and other commonly used verification technologies. This should also be the direction we should strive for.
Constraints and optimization design of FPGA
In addition to design and verification, FPGA related optimization and constraints are also important contents of advanced learning. This paper mainly includes the constraints and optimization of timing, area and power consumption. For example, when there are multiple clocks, how to write timing constraints, how to analyze timing, how to divide fixed design area, how to estimate design power consumption, and so on. This process may run through the whole FPGA project development cycle, and some common ASIC constraint methods may not be suitable for FPGA design.
Taking FPGA low power design as an example, gating clock is not necessarily suitable for FPGA. This is because the clock network in FPGA is fixed, so only the fixed clock tree or branch can be closed. If we need to do clock gating, we must control some specific clockbuffers, and at the same time, we must make sure that these clockbuffers can be controlled by logic. More importantly, we also need to ensure that the clock driven logic is within the “sphere of influence” of the clock tree, so we need to set the desired position constraint during layout and routing. It can be seen that gating clock, a common low-power design method in ASIC design, is difficult and tedious in FPGA design.
FPGA clock tree diagram
Domain related knowledge
The second part of the advanced learning path is domain specific knowledge. The reason why we want to learn this part is that FPGA does not exist alone, it needs to be applied in some specific fields and scenarios.
For example, one of the most popular applications of FPGA is the smart network card in the data center. A lot has been said about the smart network card before, including Microsoft, Alibaba, Tencent, JD, byte and many other Internet companies are laying out this technology. The essence of intelligent network card is to unload some applications originally running in CPU to FPGA for execution, which can be network protocol stack, some virtualization functions, or AI related functions, etc.
This involves a lot of domain specific knowledge, such as computer network, network function virtualization nfv, software defined network SDN, and some other virtualization technologies, such as virtio, OVS, etc.
In addition, domain related knowledge also includes a variety of high-speed interface protocols and bus related content. For example, PCIe, DDR, HBM, Ethernet, transceiver, and various bus protocols. These and FPGA also have a very close relationship, in the actual job application is also an important bonus.
When learning these contents, I personally suggest that we should combine the needs of the target position or project and study purposefully, instead of thinking of stuttering. For example, I don’t know much about using FPGA for HD video processing, because I don’t do this direction, but I probably know how to build a knowledge map and learn step by step from it. In fact, this is OK.
Vocational skills related abilities
The third point of FPGA advanced learning route is the hard power that professional engineers need to have. For example, almost all of the development environment in the enterprise is completed in the Linux system, and most of the time there is no graphical interface. So in addition to the commonly used EDA tools, we also need to master some basic commands of Linux. In addition, you should master at least one scripting language, such as TCL, Perl, Makefile, python, etc. This can greatly improve our work efficiency, which is also a necessary skill for chip engineers.
In addition, as an FPGA Engineer, the ability of hardware debugging is indispensable. A very common scene in the daily work of professional engineers is to use and debug a variety of FPGA boards, such as taking a brand new board and developing it from scratch.
This requires us to be able to read the schematic diagram of the board, know how to write various constraints, how to use various resources on the board, and so on. In addition, when the design error, how to debug the hardware, and how to design some useful logic functions to facilitate hardware testing, such as various status registers and so on. For some professional fields, such as the network field, you may also need to know how to conduct traffic testing, such as the use and configuration of dpdk, the use of some test instruments, the use of some common network analysis tools (such as Wireshark), and so on.
Generally speaking, these professional engineers need to have the hard power, which may not be able to contact during their schooling. This requires us to constantly practice and summarize in the work, in order to accumulate these skills bit by bit.
Soft power of professionals
In addition to hard power, the cultivation of soft power is also very important, including communication, time management, teamwork, leadership, and the ability of continuous learning.
No matter in the field of chip or other engineering, most of the projects are completed by many teams. Therefore, how to communicate with the members of different teams about the project content, how to make the project plan, how to grasp the project schedule, and how to solve the problems are the problems that professional engineers almost encounter every day.
In fact, no matter what career you are engaged in or intend to engage in, we should start to cultivate our soft power from now on. For example, communicate more with people, actively participate in various activities, or as I mentioned in my previous article “sharing is a necessary quality for programmers”, constantly share various experiences in my study and work. All of these will certainly be of great help to our future career.
In today’s article, we have sorted out what abilities a professional FPGA Engineer needs to possess. There are four parts, namely, advanced development skills related to FPGA, special knowledge in various fields, and necessary hard power and soft power for chip engineers. For each part of the content, we also have in-depth understanding of how to learn and improve their ability.
In fact, the professional contents mentioned here are only a part of our daily work. They may change with the development of technology and even be replaced by various new technologies. Therefore, the most important thing is to cultivate their ability of continuous learning, constantly try new technologies and tools, and strive to jump out of their comfort zone. Only in this way can they always maintain their competitiveness and realize better value of life.
Editor in charge: PJ