The first time I came into contact with the AXI 4 bus was when I was using xilinx zynq. It was a cloud of fog when I used it. Now the fog is less, but there are still many places that I haven’t touched. This article serves as my own summary. If you have any questions, you are welcome to criticize and correct.

What is the AXI bus?

AXI first appeared in AMBA 3.0 as part of the ARM AMBA microcontroller bus. After AMBA 4.0 was released, AXI4 appeared.

The AXI 4 bus, like other buses, is used to transmit bits information (including data or addresses). There are three types of AXI4 buses, namely AXI4, AXI4-Lite, and AXI4-Stream.

AXI4 is a high-performance memory-mapped bus, AXI4-Lite is a simple, low-throughput memory-mapped bus, and AXI4-Stream can transmit high-speed data streams. Literally, AXI4-Lite is a lightweight version of AXI4. The wording of memory-mapped is retained here, mainly to distinguish it from AXI4-Stream.

memory-mapped can be understood in this way, assuming there is a master A, and slave B, A and B communicate through AXI4 or AXI4-Lite connection, A can regard the peripheral device B as an address on A. When A transmits data to B, it is equivalent to A transmitting data to this address.

Unlike AXI4 and AXI4-Lite, AXI4-Stream does not require an address channel.

AXI4, AXI4-Lite, AXI4-Stream interface

The AXI4 and AXI4-Lite interfaces consist of 5 different channels: two read channels and three write channels.

Two read channels: read address channel (read address channel), read data channel (read data channel);

Three write channels: write address channel, write data channel, write response channel;

AXI4 read channel operation picture from reference [1]

AXI4 write channel operation picture from reference [1]

The read channel and the write channel are separated, so that bidirectional data transmission can be completed. In addition, AXI4 can realize burst transmission. In other words, multiple data can be transmitted after one address, up to 256 bytes. AXI4-Lite does not support burst transmission.

AXI4-Stream has only one channel, does not need an address, and can transmit unlimited data in burst.

Common Secondary IPs

AXI Interconnect IP and AXI SmartConnect IP:

As mentioned above, AXI4 and AXI4-Lite adopt the memory-mapped method, whether it is 1 master and 1 slave, 1 master and N slaves, N masters and 1 slave, N masters and M slaves , using these two ip can help us complete the mapping.


Useful when caching data, or across clock domains.

AXI Direct Memory Access (DMA) engines

When we have an IP of the AXI4-stream interface and want to connect it to the IP of the AXI4 interface, the conversion can be completed through AXI DMA.

AXI interface on ZYNQ

The picture comes from zynq 7 processing system ip

A total of 9 AXI interfaces are reserved on zynq’s ps, including two GP AXI masters, two GP AXI slaves, four HP AXI slaves, and one ACP AXI slave.

These interfaces are all AXI3 type, but using AXI4-Lite, AXI4 IP can still communicate with these interfaces, because in actual use, the software will use AXI Interconnect ip to help us complete the interface conversion.

main reference

[1] ug1037-vivado-axi-reference-guide

[2] ug585-Zynq-7000-TRM

AXI4-Stream is relatively simple in the AXI4 family. Next, we mainly answer two questions:

(1) What does the data stream transmitted by AXI4-Stream contain?

(2) What are the interface signals of AXI4-Stream? How do master and slave shake hands?

data flow

The data stream transmitted by AXI4-Stream contains three types: data type, position type, and null type.

The data type is the most meaningful data; the position type is used as a placeholder and can be used to represent the relative position of the date type, and the null type does not contain any useful information.

There are many types of data flow structures, for example: you can only transmit data, that is, all data types, excluding position type and null type; you can also mix data type and null type; you can also combine position type and data type is mixed with transmission. Of course, there is no problem in mixing and transmitting the three.

All are data type

data type and position type mix and match

So the question is, there are three types of data stream transmission, how to distinguish these three types during the transmission process? The interface signals of AXI4-Stream can help us distinguish, let’s see what interface signals are there.

interface signal

Let’s take a look at the picture first:

ACLK and ARESETn signals, needless to say, clock and reset signals;

Next is the TVALID and TREADY signals, which are sent as handshake signals from the master and slave respectively. How to shake hands? Think about it, the process of shaking hands with others can be roughly divided into three stages: both parties have some kind of psychological activity in their hearts, reaching out, shaking hands up and down; shaking hands on AXI4-Stream also generally goes through these three processes.

(1) Some kind of psychological activity is carried out in the hearts of both parties: it is equivalent to the master and the slave doing things within themselves, and they can shake hands when they are free to shake hands after finishing their own affairs. The master sends out a TVALID high signal after finishing the work, and the slave sends out a TREADY high signal after finishing the work .

(2) The process of reaching out is actually quite particular, even in real life. When you shake hands with others, the other person may extend his hand first, you may extend his hand first, or both of you may extend your hand at the same time. The same is true for master and slave. Maybe the TVALID high signal is earlier than TREADY high, maybe TVALID is later than TREADY, or it may appear at the same time.

(3) Handshake shakes up and down: When both of you raise your hands, the next step is the grand handshake stage. When shaking hands, you can feel the strength of each other’s hands… the master and slave Data transmission starts when both TVALID and TREADY are high.

TVALID respects you

TREADY respects you first

TVALID TREADY goes high at the same time

Not much to say about TDATA, it is the data stream. As mentioned above, there are three types in the data stream, namely data type, position type and null type, so how to distinguish them during transmission? Rely on TKEEP and TSTRB.

For the sake of illustration, assuming that n is the number of bytes of the data bus, that is, the number of bytes of TDATA, TDATA can be expressed as TDATA[(8*n-1):0], TKEEP and TSTRB have n bits, and TDATA on Each byte has a one-to-one correspondence, and the two together represent the type of each byte on TDATA. For example, n = 2, TDATA = 0x0036, TKEEP = 2’b01, TSTRB = 2’b01. Since the high bits of TKEEP and TSTRB are 0, the high-order byte of TDATA is null type; since the status of TKEEP and TSTRB is 1, the low-order byte of TDATA is data type.

One thing to note is that it cannot be used when TKEEP is 0 and TSTRB is 1.

TKEEP and TSTRB indicate the byte type in the data stream

The TLAST signal is used to indicate the end of a packet. For example, when sending a packet with a size of 32 bytes, when the 32nd byte is sent, the TLAST signal can be pulled high to indicate that the packet has been sent.

TID and TDEST signals: It is useful when we transmit different data streams on the same interface. Generally speaking, AXIS4-Stream Interconnect Core IP can help us complete this process. The TUSER signal is used to transmit some additional information.


[1] ug1037-vivado-axi-reference-guide.pdf

[2] IHI0051A_amba4_axi4_stream_v1_0_protocol_spec.pdf

Reviewing editor: Li Qian

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