introduction

The traditional motion control card uses single-chip microcomputer as microprocessor, through some large-scale integrated circuits to control the servo motor. Because of its complex structure, it has the disadvantages of slow high frequency response and low control precision. This paper presents a motion control card based on FPGA (field programmable gate array) and PCI9054 interface chip. The internal hardware interface and algorithm are realized by programming FPGA. In this way, the shortcomings of traditional motion control can be overcome, and the flexibility and portability are greatly improved.

Hardware structure and design

1.1 composition

The motion control card described in this paper is a PCI (peripheral component interconnect) interface card. It uses the FPGA of ep1c6q240c8 produced by Altera company as the programming logic device to realize all hardware algorithms and feedback signal detection. The closed-loop control mode of pulse plus direction is adopted to control the motor. The whole motion control card system can be described in Figure 1.

Application scheme of motion control card based on FPGA ep1c6q240c8

1.2 design

When describing and designing the hardware circuit of the motion control card, the design principle of synchronous timing is strictly followed, and the core circuit is realized by D flip-flop. The main signal of the circuit is generated by the rising edge flip-flop of the clock. In this way, the burr can be avoided well, and there is no burr in the simulation after layout and the actual working signal sampled by high-speed logic analyzer. In order to ensure the real-time performance of the frequency division output of the whole system, the ping-pong operation technique as shown in Figure 2 is used in the high-speed variable frequency division multiple data flow control. When the number of buffer cycles is odd (2n + 1), the input data stream is buffered to ram I and fetched from RAM II to the operation module. In the even number (2n) buffer cycle, the data stream is buffered to ram II, and the data in ram1 is sent to the final frequency division and counting operation module for calculation and output through the selection of “data output selection unit”. It’s a cycle. This pipeline algorithm can accomplish seamless data buffering and processing.

The motion control card described in this paper involves four modules: bus controller, frequency divider, timer and feedback control. The schematic diagram is shown in Figure 3. The bus controller completes the arbitration logic, address decoding and data flow control of PCI9054 local bus, so that the data on PCI data bus can be correctly decoded to each sub control module for operation and output. The timer realizes hardware timing. The computer inputs a time value and a control word indicating the start of timing to the motion control card through the driver. The motion control card starts timing. When the timing is completed, it enters the interrupt service program through the hardware interrupt mode [6], so as to realize the accurate positioning of the motor angle. We can also use some user codes as interrupt processing subroutines to realize the function of timing switching or operation. The frequency divider realizes the frequency division of working frequency (40MHz) and obtains the pulse frequency of controlling motor speed. The feedback control module realizes the output compensation and state monitoring function of the motor, which can be corrected by reading the error, so as to improve the control accuracy of the system. These modules are described in the way of schematic diagrams and VHDL language in FPGA, which makes the logic level clearer and more readable.

2 algorithm design

2.1 real time frequency division algorithm

The motor speed can be controlled by different pulse frequency output from the motion control card, so the response speed of the pulse frequency determines the control accuracy of the whole motor. This requires us to fully consider the real-time performance of the frequency division algorithm when designing the algorithm. This paper proposes a frequency division algorithm based on adding two counters, which can solve this problem well. The specific flow chart of the algorithm is shown in Figure 4. The PLL output clock is used as the global clock, and two single port RAM are used to refresh the frequency division multiples. The plus two counter counts the rising edge of the input clock, and compares and judges the count value. If the count value is greater than or equal to twice the frequency division multiple, the output is “1”, otherwise it is “0”. The function of frequency divider is realized. The output of frequency divider is the pulse (CLK) of motor speed controlled by motion control card_ out)。

2.2 closed loop control algorithm

The whole motion control card adopts the control mode of pulse plus direction to realize the control of motor speed and direction. In order to ensure the control accuracy of the motor, when the motion control card outputs the pulse to the motor driver, the motion control card reads the feedback pulse and direction from the encoder. In this way, as long as two counters are designed to count the output pulse and feedback pulse at the same time, and the count values of the two counters are judged and calculated, and then the circular interpolation is carried out according to the calculated difference value, the closed-loop control of the motor can be realized.

3 debugging and simulation results

3.1 system commissioning

This card uses signaltap Ⅱ of Quartus Ⅱ software for simulation debugging. It is an embedded logic analyzer based on logic analysis core. In use, the debugging personnel can analyze and judge the system fault by capturing all the signals and nodes inside the FPGA device without external special instruments. The whole debugging process is very intuitive and convenient. Signaltap II collects data at the rising edge of the acquisition clock. If the acquisition clock is not set properly, sometimes the unexpected data state that can not accurately reflect the design can be obtained. Altera suggests that the global clock is the best choice. In this paper, the global clock gclk is used as the acquisition clock, level 1 trigger, and result = eld ({hold, 1}) is used as the trigger logic. The running analysis results are shown in Figure 5. It is worth noting that after debugging, the signaltap II file needs to be removed from the design directory to avoid wasting resources.

3.2 debugging results and error analysis

From the debugging results in Figure 5, the whole control of the motion control card is subject to the bus arbitration logic. The data exchange between PCI and FPGA is carried out when ready = 0, and the data on bus LD is valid when ready = 0. When the register value of frequency division multiple is changed, the output frequency of frequency division will be changed immediately to meet the design goal. To detect and judge the external signals such as motor travel (journey 1 and journey 2), alarm, zero and servo. The feedback clock is detected and counted. The data exchange between PCI and FPGA takes place at the rising edge of the system clock. Therefore, in the process of data exchange, there must be a delay error less than one clock cycle.

4 Conclusion

The motion control card described in this paper has the following characteristics: ① the data input and output port adopts optical isolation technology to avoid some unnecessary interference; ② FPGA adopts independent 40MHz clock and phase-locked loop design to ensure the clock stability of the system; ③ using plus two frequency division algorithm to improve the real-time performance of the frequency division output; ④ FPGA As the core processing chip, the hardware cost is reduced, the hardware design is simplified, and the real-time performance is improved; ⑤ the state detection and error correction of the motor are realized through the state detection and feedback module; ⑥ the interrupt timing module is designed to realize the angle control of the motor.

Editor in charge: GT

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