1 Introduction

In the development process of the missile model, the matching device is the key component for signal conversion in the telemetry system, and it is the throat that sends the information of all key components on the missile to the telemetry equipment. The accuracy and reliability of the matching device are important factors that affect the telemetry results. This topic is to provide high-precision signals for the automatic test system of the telemetry matching device, which is used to check the working condition of the automatic test system of the matching device. In this sense, the design and implementation of miniaturized and generalized signal cards are an inevitable requirement of the test platform. Therefore, advanced design methods and large-scale programmable logic devices must be used to adapt to this development trend. The development of large-scale programmable logic devices such as CPLD/FPGA and the maturity of VHDL hardware description language have laid a good foundation for this. Hardware basics. In order to improve the precision of the signal card, the choice of D/A is very important. The 16-bit D/A converter AD768 of Analog Device Company is selected to fully meet the design requirements of precision.

This paper mainly introduces a scheme based on FPGA and AD768, using VHDL hardware description language to design and implement a high-precision signal card. Theory and experiments prove that the scheme is feasible.

2 Scheme design of signal card

2.1 Function introduction

The output of the signal card is 64 adjustable voltages of -15V~+15V. The adjustment accuracy of the signal is not less than 0.1%. The driving current of each signal is not less than 5mA and not more than 20mA. In addition, according to needs, the limit output range can also be arbitrarily selected by adjusting the hardware within the range of -15V to +15V. The smaller the voltage range, the smaller the absolute error voltage.

2.2 Block Diagram of Signal Card

The signal card is composed of FPGA main control unit, single-chip microcomputer, power supply module, large-capacity memory, DAC, subsequent conditioning circuit and output interface. Among them, the waveform data is generated by the host computer through software programming, and the data is transmitted to the high-speed digital bus through the main control card. The signal card is received by the single-chip microcomputer through the bus interface and then sent to the FPGA, which is sent to the large-capacity memory for storage. The central control logic of the FPGA is responsible for the generation of various control signals. It controls the data output from the large-capacity memory to the DAC conversion, and controls the gating of the analog switch. The principle block diagram of the signal card is shown in Figure 1.

The power supply module supplies power to the various parts (arrows not marked in the figure). The control signal of the relay is given by the host computer, transmitted to the digital bus through the main control card, and then sent to the relay through the single-chip microcomputer and FPGA. The relay controls the power supply of the subsequent conditioning circuit, so as to control whether to output the signal to the external device.

2.3 Some measures to improve accuracy

Using 16-bit D/A can achieve the required adjustment accuracy of 1%, but due to a series of interferences such as crosstalk and noise in signal transmission, it will inevitably affect the accuracy. In view of this, we add the following measures to the circuit to Suppress interference and improve accuracy.

1. The circuit board adopts 4-layer board design to improve the anti-interference ability of the whole system

2. The analog ground and digital ground are separated and connected at one point with a 0 ohm resistor. The entire signal source module does not share the ground with other modules of the test bench.

3. Use an optoelectronic isolator to isolate the interface and the microcontroller to suppress interference.

4. Adopt independent power supply to supply power to the amplifier circuit through the relay to ensure that the power supply voltage is not disturbed.

5. The subsequent conditioning circuit adopts the external frequency compensation method to reduce the loop gain and improve the stability of the signal.

It has been verified that the above measures have well suppressed the system ground interference and played a great role in improving the system ground adjustment accuracy.

3 DAC unit circuit design

AD768 is a 16-bit high-speed analog-to-digital converter with a conversion rate of up to 30MSPS. According to requirements, the output analog signal voltage range is required to be between -15V and +15V. The conversion circuit adopts the combination of AD811 and AD824, as shown in Figure 2.

In Figure 2, IOUTA is the current output of the AD768, and the digital input is all 1 when the full scale; REFOUT is the reference output voltage of the AD768, with a value of 2.5V. The AD768 has two complementary current outputs, IOUTA and IOUTB, which have the same dynamic performance. Can be configured as single-ended or differential two operating modes. IOUTA and IOUTB can be converted to complementary single-ended voltage outputs VOUTA and VOUTB through a load resistor R1. The differential voltage exists between VOUTA and VOUTB, and a differential amplifier is used to convert the differential signal into a single-ended voltage. This design uses the differential mode of AD768. By setting the value of IBipolar to half of the maximum feedback current IFB, the boundary value of the output voltage is made symmetrical. When the reference output voltage REFOUT terminal is grounded, the AD768 is in the current output mode, and the relationship between the output current IOUTA and the reference current IREFIN is:

IOUTA=(DACCODE/65536)×(IREFIN×4) (1)

In formula (1), DACCODE is a 16-bit digital input code, which changes between 0 and 65535. The value of IREFIN is 5mA. Therefore, the maximum output current IOUTA will not exceed 20mA, which can meet the requirements of the required driving current. After the output current is buffered and amplified by the operational differential amplifier AD811, the output voltage range is -2.5V ~ +2.5V, and then through the amplification circuit with the amplification gain of 6, the output voltage VOUT will be between -15V ~ +15V, which can meet the specified Require.

4 FPGA internal logic control

VHDL language is a hardware description language with strong description ability, which can cover many fields and levels of logic design, and supports many hardware models. Compared with other HDL languages, it has: complete design technology, flexible methods, and extensive support; strong system hardware description capability; can be programmed independently of the process; language standards, specifications, easy to share and reuse; shorten the design cycle and reduce investment risks Etc. The FPGA internal logic of this design is all written in VHDL language.

4.1 FPGA Internal Schematic

Figure 4 is the internal schematic diagram of the signal card FPGA implemented by VHDL language. Driven by the system clock signal (FOSC), the FPGA judges the control signal given by the host computer, receives the waveform data sent by the host computer, and then outputs various control signals , and send the data to the memory. In addition, the FPGA also gives the control signal of the indicator light, and indicates its working status through the indicator light, which facilitates the judgment and debugging of the working status of the equipment.

4.2 Secondary encoding of data

Since the data transmission between the MCU and the FPGA is 8-bit, and the D/A we use is 16-bit, the problem lies in the transmission of the 16-bit data generated between the MCU and the FPGA. The 16-bit data is divided into three 8-bit data, and the combination of the upper two bits of each data, that is, DATA7 and DATA6, indicates whether the data is high, middle or low. The 8-bit data transmitted by the single-chip microcomputer to the FPGA, the FPGA should restore them to the original 16-bit data, which is the secondary encoding of the data. The secondary encoding of data is the focus of the entire program. FIG. 5 is a flowchart of secondary encoding.

In the process of bus writing (that is, wr is valid), the FPGA needs to determine whether the data received from the microcontroller is high, middle or low. In the program, busdata (7 downto 6) = "00" indicates that the received data is low; busdata (7 downto 6) = "01" indicates that the received data is the middle bit; busdata (7 downto 6) = "10" indicates that the received data is the high bit. The FPGA integrates three 8-bit (actually 6-bit) data, and the data written into the memory and received by the D/A converter is the converted dataout [15 … 0].

5 Conclusion

The output result of the signal card is shown in Figure 6. It can be seen from the figure that the waveform is stable and the distortion is extremely low, which well meets the design requirements.

Therefore, it is feasible to use programmable logic device FPGA and 16-bit D/A converter AD768 to design the scheme. This signal card has simple structure, stable performance, high effectiveness and reliability, and is easy to modify and optimize. Advantages, shorten the development and design cycle.

The innovation of the article: The signal card based on FPGA and AD768 designed in this article can generate waveform signals with adjustable amplitude from -15V to +15V, and the adjustment accuracy is as high as 1%, which is much higher than that of ordinary signal sources; stable performance and high reliability , easy to modify and optimize.

Responsible editor: gt

Leave a Reply

Your email address will not be published.