AHB overview

AHB (advanced high performance bus) is a part of AMBA (advanced microcontroller bus architecture) bus on chip system. In SoC chip, AHB bus is mainly used to interconnect components with high performance requirements, such as CPU, on-chip high-speed ram and DMA.

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Figure 1ahb protocol evolution

As shown in Figure 1, AHB protocol is proposed in amba2. Along with the evolution of AMBA protocol family, AHB is joined_ Lite,AHB5Lite。 This paper introduces the difference between ahb2 and ahahb2.

AHB application block diagram

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Figure 2ahb bus application block diagram

Continue to use the application block diagram used in the previous article to introduce APB interface. As shown in Figure 2, AHB bus is mainly used for interconnection between high-performance ARM core, high bandwidth ram on chip, DMA, high bandwidth memory interface and APB bridge.

AHB bus structure

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Figure 3 AHB bus structure

AHB bus consists of ahbmaster, ahbslave and basic components. The basic components include: arbiter, decoder. AHB is a multi master bus, which is significantly different from APB single master bus. In order to solve the problem of multi bus access to peripherals, arbiter is introduced for arbitration, and decoder is responsible for the address decoding between slaves.

AHB bus interface signal

AHB bus signals are shown in Table 1

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Table 1ahb interface signal (1)

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Table 1ahb interface signal (2)

The signals in red font in the table are the differences between different versions of AHB bus. It is summarized as follows:

The bit width of hprot is different: ahb5lite is 7bit, ahb2 and ahblite are 4bit.

Different bit width of hresp: ahb2response is divided into four types: OK, error, retry and split, which need 2bit indication. Ahblite / ahb5lite simplifies it to two types: OK and error. It can be indicated by 1 bit width.

Different bus topologies: ahb2 can access multiple masters through arbiter. Ahblite and ahb5lite delete arbiter and only define single master access. The bus structure is shown in the figure below.

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Figure 3ahblite bus structure

In order to solve the multi master application of ahblite and ahb5lite, the concept of multilayer is introduced to expand the multi master in amba3. The expansion mode is shown in the figure below:

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Figure 4 bus structure of ahblitemultilayer

For students interested in multilayer, please refer to the third material in the resources at the end of the article.

AHB basic transmission

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Figure 5 AHB basic read transfer

AHB transmission is divided into two stages: address stage and data stage. Figure 5 shows a typical zero wait read transfer. In the address phase, master sends read access to Salvea, and slave returns data (a) in the data phase. Pay attention to the details in the figure. In the slave data phase, the master also initiates the write access of slave. This pipeline access behavior is the reason why AHB performs better than APB.

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Figure 6ahb basic write transfer

Figure 6 shows zero wait for write transfer. In the address phase, write access is initiated to slaveA, and write data is sent in the data phase.

Postscript

In order to improve its performance, AHB bus introduces pipeline transmission mode relative to APB bus. In this way, the theoretical performance of AHB bus is twice that of APB bus in the case of the same frequency and data bit width. AHB bus protocol is much more complex than APB bus protocol. This paper only makes an introduction. Interested students can refer to the reference materials at the end of this paper for in-depth understanding.

Editor in charge: CC

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