NAND flash memory has become a mature technology, and various formats available now have been adopted in many industrial applications.

However, in the hope of surpassing the standard options, APACER has developed some optimizations of NAND flash technology. The purpose of these optimizations is to provide customers with the P / E cycle most suitable for their applications.

Previously, the company developed an optimized form of NAND flash memory called SLC Lite. The central concept behind SLC Lite is to make 2D MLC behave like SLC. MLC contains 2 bits, but by programming only 2 bits (least significant bit (LSB)), the behavior of cell distribution is almost the same as that of SLC flash memory. Then, the durability is greatly improved to 20000 P / E cycles. The standard 2D MLC can only reach 3000 P / E cycles.

However, with the maturity of 3D NAND flash memory technology, the company’s engineers have developed a process similar to SLC Lite for 3D NAND drives. Two new forms of this technology are called SLC Litex and MLC Litex. SLC Litex is based on 3D NAND. The company’s engineering team adjusted the firmware to provide the maximum number of P / E cycles – 30000 in this format, which is ten times that of MLC or industrial 3D TLC. The longest service life and reasonable price.

MLC Litex is also based on 3D NAND technology. The firmware is fine tuned to provide more than three times the P / E cycle (10000) of MLC or industrial 3D TLC. While prolonging the service life, the cost-benefit optimization is realized.

The standard bit format of 3D NAND TLC stores 3 bits in 1 cell. MLC Litex only programs 2 out of 3 bits. Therefore, the capacity of MLC Litex is reduced by only one third. The advantage of this trade-off is that it increases the P / E cycle. According to this idea, SLC Litex only programs one of the three bits. Therefore, the capacity is reduced by two thirds, but more P / E cycles can be used.

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