FPGA has synchronous reset and asynchronous reset. Its advantages and disadvantages are as follows.

Advantages of synchronous reset: A. It is conducive to the simulation of the simulator. b. The designed system can become 100% synchronous sequential circuit, which is greatly conducive to timing analysis, and the synthesized Fmax is generally high. c. Because it is only effective when the clock effective level comes, it can filter out burrs higher than the clock frequency.

However, it has many disadvantages, mainly including the following: a. the effective duration of the reset signal must be greater than the clock cycle in order to be truly recognized by the system and complete the reset task. At the same time, factors such as CLK skew, combinational logic path delay, reset delay and so on should be considered. b. Because the DFF in the target library of most logic devices only has asynchronous reset port, if synchronous reset is adopted, the synthesizer will insert combinational logic into the data input port of the register, which will consume more logic resources.

Analysis on the principle of asynchronous reset and synchronous release in FPGA

For asynchronous reset, it also has three advantages, which are corresponding: A. most DFFs of the target device library have asynchronous reset ports, so asynchronous reset can save resources. b. The design is relatively simple. c. Asynchronous reset signal identification is convenient, and it is convenient to use the global reset port GSR of FPGA.

However, the disadvantages of asynchronous reset: A. problems are easy to occur when the reset signal is released. Specifically, if the reset release is just near the effective edge of the clock, it is easy to make the register output metastable, resulting in metastability. b. The reset signal is easily affected by burrs.

Based on the above, it is better to perform an “asynchronous reset and synchronous release” process before sending the global reset signal. You can use rst_ NR is used as a reset signal for asynchronous reset, which will not cause metastable state, and can be reset by using the reset signal of the trigger itself, which will not waste FPGA resources.

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