In the process of developing Ethernet interface, we often see MII, RMII, gmii, rgmii and other abbreviations. Before developing an interface, make these terms clear.

Analysis of the total process of developing Ethernet interface

1MII

The abbreviation of MII (medium independent interface) is translated into Chinese as “media independent interface”. This interface is generally used between MAC layer and PHY layer of Ethernet hardware platform. There are many types of MII interfaces, including MII, RMII, smii, SSMII, gmii, rgmii, sgmii, TBI, rtbi, XGMII, XAUI, xlaui, etc.

MII supports 10 MB and 100 MB operations. An interface consists of 14 wires. Its support is flexible, but there is a disadvantage because it uses too many signal wires for one port

Analysis of the total process of developing Ethernet interface

RXD (receivedata) [3:0]: data receiving signal, 4 signal lines in total;

TX_ Er (transmitterror): send data error prompt signal, synchronized with TX_ CLK, high level valid, indicates TX_ Invalid data transmitted during ER validity period. For 10Mbps rate, TX_ Er did not work;

RX_ Er (receive error): receive data error prompt signal and synchronize with Rx_ CLK, high level valid, indicates Rx_ Invalid data transmitted during ER validity period. For 10 Mbps, RX_ Er did not work;

TX_ En (transmitenable): send enable signal, only in TX_ The data transmitted within the validity period of en is valid;

RX_ DV (receive data valid): receive data valid signal, and act on TX of transmission channel_ EN;

TX_ CLK: transmit reference clock, clock frequency is 25MHz at 100Mbps, clock frequency is 2.5MHz at 10Mbps. Attention, TX_ Therefore, the PHY side is provided from the clock to the Mac.

RX_ CLK: receive data reference clock, clock frequency is 25MHz at 100Mbps, clock frequency is 2.5MHz at 10Mbps. RX_ CLK is also provided by PHY side.

CRS: carrier sense, carrier detection signal, does not need to be synchronized with the reference clock, as long as there is data transmission, CRS is effective, in addition, CRS is only effective in half duplex mode;

Col: collision detectd, collision detection signal, does not need to be synchronized with the reference clock, only PHY is effective in half duplex mode.

There are 16 wires in the MII interface.

2RMII

RMII is a simplified MII interface, which has twice less signal lines than MII interface in data receiving and sending. Therefore, it generally requires a 50 megabyte bus clock, which is twice the MII interface clock.

Compared with MII interface, gmii’s data width changes from 4 bits to 8 bits, and the control signal in gmii interface, such as TX_ ER、TX_ EN、RX_ ER、RX_ The functions of DV, CRS and col are the same as those in MII interface, which send the reference clock GTX_ CLK and RX_ The frequency of CLK is 125MHz (1000Mbps / 8 = 125MHz).

Here is a special note, that is to send the reference clock GTX_ CLK, it and TX in MII interface_ CLK is different from TX in MII interface_ CLK is provided by PHY chip to MAC chip, while GTX in gmii interface_ CLK is provided by MAC chip to PHY chip. The two directions are different.

In practical application, most gmii interfaces are compatible with MII interface, so the general gmii interface has two transmit reference clocks: TX_ CLK and GTX_ CLK (the directions of the two are different, as mentioned earlier). When it is used as MII mode, TX is used_ CLK and 4 of the 8 data cables.

Gmii is the MII interface of gigabit network. Gmii uses 8-bit interface data, working clock 125MHz, so the transmission rate can reach 1000Mbps. At the same time, it is compatible with the 10 / 100Mbps working mode specified by MII.

The rgmii interface represents a simplified gmii interface. Rgmii adopts 4-bit data interface, working clock 125MHz, and transmits data at both rising and falling edges, so the transmission rate can reach 1000Mbps. At the same time, it is compatible with the 10 / 100Mbps working mode specified by MII, supports the transmission rate of 10m / 100M / 1000mb / s, and its corresponding CLK signals are 2.5mhz/25mhz/125mhz.

Editor in charge: PJ

Leave a Reply

Your email address will not be published. Required fields are marked *