Moore's Law has not failed, and the EDA industry has been challenged to remain profitable. Remaining profitable requires a shift in focus from silicon structure design to system generation.
● Advances in processing technology are challenging traditional ASIC design methods.
• Clustering using application processing units will shift the development burden to the software.
● ESL will be the fastest growing segment of the EDA market.
● Designers will increase the use of FPGAs and structured ASICs in the system.
The EDA industry is a service industry. The way it grows depends on the direction and strength of the industries it serves. The semiconductor industry has been and will always be the primary driver of EDA growth. Consumer products have replaced IT (Information Technology) as the second most important driving force that has a decisive influence on the types of products developed by EDA companies. These two dynamics have created a major shift in the demand for EDA tools, and as a result, the types of EDA industry tools are facing a major shift to meet new markets and additional demands.
The semiconductor industry is impacting the EDA industry with new capabilities enabling the fabrication of smaller and smaller transistor geometries. This evolution is not new. Scientist Gordon Moore said 40 years ago that the number of transistors on a device would double every 18 months. The semiconductor industry was quick to refer to this discourse as "Moore's Law." Moore's predictions have so far come true, with semiconductor manufacturing capabilities reaching the processing routines, or nodes, that make smaller and smaller transistors on a single wafer, thereby improving processing technology. Predictions of achievable processes suggest that Moore's Law will remain valid for at least the next 6-8 years. In almost all cases, semiconductor fabs can achieve the predicted doubling of transistor counts simply by making smaller transistors on a single chip than in previous processes, and by temporarily increasing the chip size. Whether the number of transistors will continue to double over the next 10 years is unclear and will depend on new technologies rather than continuous improvements to existing methods.
Evolution in the new century
At the turn of the millennium, engineers could optically form geometries with nominal 0.18-micron geometries to fabricate devices. Until then, the size required for the design was the most challenging hurdle for engineers. However, the larger the design you make on a chip, the more complicated the problem becomes. EDA tools must be able to handle both large design databases and design hierarchies. Engineers use a hierarchical approach to divide the design into many manageable parts. Each part is a unit, containing a function and a well-defined interface. To deal with the complexity of each unit, engineers use HDL (hardware description language) that supports RTL (register transfer level) abstraction, such as Verilog or VHDL. Logic synthesis tools convert this description into a netlist of gates using a library of basic logic blocks specific to the factory that produces the device, and place-and-route tools generate the topology needed to fabricate the mask to produce the device. This approach applies almost without exception to the 0.18-micron process node.
In 2002, semiconductor technology took another step forward and began supporting 0.13-micron feature sizes. On the surface, this step is almost a normal evolution of the manufacturing process. However, this step introduced a major mutation, which required new design and manufacturing methods and created many new problems. Light source wavelengths required to expose circuit patterns on photoresist are smaller than visible light, so manufacturers use RET (reticle enhancement) and OPC (optical proximity correction) techniques to achieve the required line sharpness, thus requiring EDA Tools Support new manufacturing methods with new or enhanced DFM (Design for Manufacturability) tools.
Many other consequences of smaller transistor geometries have a greater impact on the design approach. Two factors in particular require new development tools: the size of the logic gates, which are now generally smaller than the traces that interconnect the gates, and the fact that the width of the traces is sometimes smaller than the height of the traces. In the first case, engineers must use new tools to correctly predict the physical and logical behavior of the circuit; in the second case, engineers need to consider parasitic effects, which can turn the traces into antennas. EDA vendors must develop a new set of tools to support designers in 0.13-micron processes. Physical synthesis replaces logical synthesis. Physical synthesis tools work in conjunction with place-and-route tools to determine the topology of the circuit, since both the functional and physical properties of the resulting circuit affect the correctness of the circuit. In 2004, leading designers were already designing ICs on the 90-nanometer process, and semiconductor manufacturers demonstrated experimental circuits fabricated on the 65-nanometer process. 65nm technology could be used to fabricate devices as early as late 2005.
From Moore's Law until the 0.13-micron process node, designers only need to understand logic design to design practical ICs. Today, because of the use of physical synthesis, designers must understand the fundamental laws of physics that govern circuit behavior. Unfortunately, very few designers are well trained in this area in college. This situation places a significant burden on EDA tools, including helping users solve problems they don't fully understand. While EDA manufacturers have and continue to devote significant resources to the development and improvement of new tools, the gap between the semiconductor industry's manufacturing capabilities and the ability of designers and EDA tools to efficiently and economically develop circuits is increasing. big. This situation leads to underutilization of semiconductor fabs, which ultimately increases wafer costs.
Consumer products, especially communications and graphics equipment, have replaced computing engines and information storage products as a major market for system manufacturers. These systems companies are EDA suppliers' most important customers, and their technical and economic needs directly affect the rise and fall of the EDA industry. The difference between consumer products and IT products is that consumer products have a relatively short market window and are more sensitive to price competition. For a company to be successful, it must develop products quickly, typically in less than a year, and recover development costs fast enough so that the product has a chance of being profitable. Using data from IBS, a research firm, Cadence Design Systems chairman and CEO Ray Bingham predicts that a typical product made on a 90-nanometer process would require an investment of $55 million to cover NRE (non-recurring engineering) costs. A company looking to achieve its normal goal of 10 times its investment in revenue depends on the product to generate $550 million in revenue. As the consumer market continues to demand new features and novelty products, companies must develop a large product market and generate revenue quickly to compensate for development costs. Over the life of a product's market, 15 times the investment will generate $825 million in revenue. When you consider that the typical market life of a consumer product is less than 18 months, few companies can meet the first of the two goals, let alone the second.
When a solution to a problem is too difficult to achieve, most engineers try a different approach. Even at the 0.13-micron process node, SOC (system-on-a-chip) device designers are increasingly using software to implement desired functions. IBS Corporation calculated the average development costs for software and hardware for various process nodes. While features are shrinking, the percentage of software development continues to increase as feature size shrinks, and software development costs grow proportionally. The 0.13-micron manufacturing process already provides operating characteristics that allow processors to maintain execution speeds fast enough to allow engineers to replace hardware with software for many functions. Of course, where execution speed is critical, dedicated hardware is still a better choice. However, these situations, which were once common enough to be a requirement for the entire ASIC industry, are now becoming less common.
When the 65nm process technology and smaller size process technology is capable of mass production, its processing speed will make it possible to use dedicated processing units in most cases. Designers will be able to include several processing units and enough memory to store complex applications on a single chip. To ensure the highest processing speed and suitable bandwidth, the processing units must communicate over a network because a bus would be too large and would constitute a challenging physical structure to manufacture while avoiding the associated parasitics. COD (clusters on die, monolithic cluster) will replace SOC. Several APUs (Application Processing Units) communicate via the on-chip network and cooperate to provide the processing power required to implement a system. Two common instances of a COD architecture. The upper part shows a common solution; the lower part shows a more specialized architecture, where the APUs have dedicated memory, or can share a dedicated memory space.
In addition to some processing units and memory, engineers also deal with certain custom areas on the chip that can be used to implement various functions centered on the hardware. The choice of technology for this area will be different due to the combined influence of classic ASICs and structured ASICs. If the computing power of the cluster is available on the chip, it is unclear whether it will need to be reprogrammable. It is very likely that this "chip" will actually consist of at least two pieces — one containing digital logic circuits and one containing analog circuits. This physical division would be necessary to make digital and analog logic circuits separately using different processes. This approach has several advantages: it continues to benefit from new machining techniques; it uses large macroblocks; it allows the user to upgrade the product through reprogramming, thereby reducing the cost of a product family over the life of the market .
Companies that have been in the general CPU business, such as Intel, AMD, TI, Motorola, and IBM, may enter the COD market and provide powerful computing platforms, and various system companies may use mainframes first and then use them. Microcomputers, and finally microprocessors, use these platforms. The designer's main job will shift from designing silicon gates to designing methods that are mostly implemented in software. This approach, while revolutionary at first glance, is actually an evolution of various technologies and markets developed over the past few years. These technology and market areas include reconfigurable instruction processors, IP (intellectual property) development and sales, software/hardware co-design (also known as ESL design, or electronic system-level design), structured ASICs, and reconfigurable hardware system.
IBM has gained valuable experience in the IP market through a distribution agreement with Xilinx that includes the PowerPC core. Although most of the feedback is only from FPGA products, customers are also using FPGAs in ASIC products. In the field of processor cores, ARM's standard processor cores are leading, while Tensilica's configurable processors are second to none. In addition, CoWare's LisATek family of products can help designers develop special-purpose processors. Tensilica reports that it has several customers using up to six configurable processors on a single chip and modifying the instruction set to produce specialized processors. Synopsys is focusing its forays into the IP market. "System design is the systematic iterative use of IP," said Aart de Geus, chairman and CEO of Synopsys. Designers likely used IP to fill most of the available space in the configurable portion of the COD. This way, they can take advantage of proven cores to reduce development time and increase reliability.
Arteris is developing monolithic networking technology based on a patented switch fabric approach to manage multipurpose packets. The company claims that its solution is compatible with many commercial bus protocols, including OCP and AMBA. To achieve yield levels that make products profitable, semiconductor manufacturers, EDA vendors, and end users will have to collaborate on product development because of design decisions made early in the workflow when using VDSM (Very Deep Submicron) manufacturing processes Will affect the degree of manufacturability of the product. Designers must become more familiar with manufacturing processes, and manufacturing engineers must learn to evaluate trade-off design costs. As you can see, the VDSM project is complex and will require significant investment not only in development, but also in training and project management. So, in most cases, it makes more sense to make programmable standard parts than to simply make ASIC devices.
Evolution of ASIC Design
Speaking at this year's EDAC (Electronic Design Automation Forum), Virage Logic's President and CEO Adam Kablamian pointed out that while EDA is the smallest area of the electronics industry, all other areas depend on its capabilities to succeed. The advent of COD products will increase the size of the EDA market, as the demand for software application development for these products will more than compensate for the decline in DFM tool sales. Kablamian also expects that some of the revenue associated with the semiconductor space will shift to the EDA space as suppliers in the EDN space enter the SIP (semiconductor intellectual property) market. SIP is a new term that replaces "hard macro" to describe those cores that are sold in a "make now" format. The advantage of SIP is that semiconductor manufacturers have proven the manufacturability of SIP, so system architects can immediately integrate SIP into a design without worrying about yield. SIP vendors will need to provide behavioral models of the various cores, and both TenisonEDA and Carbon Design provide tools that produce executable models that both companies can market while still protecting the IP value of the original design.
The big change in the distribution of supplier product revenue will be the increase in the revenue of front-end tools and the decline in the revenue of back-end tools. Gary Smith, principal analyst at Dataquest, predicted a few years ago that the ESL market would expand and diversify quickly. Increased design complexity requires engineers to work at a higher level of abstraction than RTL, and for different, but important, complexity reasons, semiconductor manufacturers must increase control over back-end translation. The complexity of optimizing a design for manufacturability has made RTL handoff a standard. Few semiconductor manufacturers support this approach, as many customers still believe they must be directly involved in the placement of chips. But it has become increasingly clear that once designers have verified the functional characteristics of a design at the abstraction level of physical synthesis input, engineers familiar with manufacturing issues are better able to deal with synthesis and place-and-route issues. The best people to do this kind of work are semiconductor manufacturers, not systems companies. Structured ASIC devices, by their very nature, require RTL handover.
Behavioral synthesis is also undergoing a transformation. First, the industry is using the word "behavior" incorrectly. According to Merriam-Webster's online dictionary, there are three basic definitions of "behavior", all of which relate to living organisms (human or animal). The hardware doesn't behave, it runs. Manufacturers should refer to tools that transform algorithm descriptions into hardware implementations as "algorithmic" synthesis. Using MathWorks' Matlab and Simulink models as input, rather than traditional HDL models, is showing promise in DSP design in this area. For years, designers have used these tools to develop DSP algorithms and then had to re-enter the design using Verilog or VHDL to complete the design synthesis. Accelchip pioneered the use of Matlab as the input for DSP synthesis, CatalyTIc followed suit, and Synplicity now has tools that generate gate-level representations of designs directly from Matlab and Simulink descriptions.
Despite advances in formal verification techniques, verification remains a major concern. Jasper Design expands the scope of formal verification by addressing the verification of a design specification rather than its implementation. To better support functional verification, Mentor Graphics has introduced a scalable verification product that supports digital, analog, mixed-signal, and software/hardware emulation environments; Cadence has introduced a multilingual Incisive verification platform; Synopsys is taking the lead SystemVerilog, the language of choice for exploring electronic systems design. Co-Ware tried to capitalize on its leadership in the SystemC market, but the SystemC language's ability to correctly simulate asynchronous and parallel hardware events was limited, so engineers used it only to develop a subset of digital designs. Some EDA companies need to make greater efforts to understand the verification needs of software engineers in order to take advantage of the growing proportion of software content in system solutions. Because many of the consumer products that are driving and will drive the electronic systems market depend on connectivity, companies specializing in RF design, such as AWR and Agilent Eesof, are likely to play a significant role in increasing EDA earnings.
When the process size is less than 90 nanometers, the FPGA and structured ASIC market will grow while the traditional ASIC market will decline. While Xilinx is focused on developing FPGAs, Altera has entered the structured ASIC market. The manufacture of FPGAs is controlled by the manufacturer, while the device structure is standard. Therefore, once designers develop and validate a process, engineers can use it to produce FPGA devices. Therefore, designers will enjoy the benefits of using programmable devices with increasing speed and capacity at will. The tools to develop systems using FPGAs will be as complex as the tools used to develop ASICs today. As a result, it will become increasingly inadvisable for FPGA vendors to develop their own proprietary tools, with the exception of place-and-route tools. Traditional EDA vendors, such as Mentor Graphics and Synplicity, have proven this market to be lucrative. Synopsys is again trying to increase this market share, and new entrants to the market, such as Celoxica, Accelchip and CatalyTIc, are introducing FPGA design technology. While the growth of ASIC tools is decelerating and `will eventually change from growth to decline, new application areas are emerging. The EDA market will change with the nature of its customers, but the overall market will undoubtedly continue to grow.
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