PCB interconnect design technology includes testing, simulation and various related standards. Testing is the method and means to verify various simulation analysis results. Excellent test methods and means are the necessary conditions to ensure the design and analysis of PCB interconnection. For the traditional signal waveform test, we should mainly pay attention to the length of probe lead to avoid unnecessary noise introduced by pigtail. This paper mainly discusses the new application and development of interconnection testing technology.

In recent years, with the continuous improvement of signal rate, the test object has changed significantly, which is no longer limited to the traditional use of oscilloscope to test signal waveform. Power ground noise, synchronous switching noise (SSN) and jitter have gradually become the focus of PCB interconnection design engineers. Some instruments in the field of RF have been applied to PCB interconnection design. The commonly used test instruments in PCB interconnection design include spectrum analyzer, network analyzer, oscilloscope and various probes and fixtures used by these instruments. In order to adapt to the increasing signal rate, the use methods of these test instruments have changed significantly. Taking these test instruments as tools, this paper mainly introduces the development of PCB interconnection design and test technology in recent years from the following aspects.

1. Calibration method of test

2. Modeling method of passive components

3. Power integrity test

4. Test method of clock signal jitter

At the end of the article, the development of future testing technology will also be briefly introduced in combination with the just concluded designcon 2005 conference.

calibration method

Among the three commonly used test instruments, the calibration method of network analyzer is the most rigorous, followed by spectrum analyzer, and the calibration method of oscilloscope is the simplest. Therefore, we mainly discuss the calibration method of network analyzer. There are three common calibration methods for network analyzer, thru, TRL and sol.

There are three methods, thru, TRL and salt

The essence of thru is normalization. When calibrating, the network analyzer records the test results of the fixture (S21_ C) , in the actual test, the test results are directly (S21_ M) And S21_ Divide by C to obtain the test result of the piece to be tested (S21_ A)。 Thru calibration ignores the reflection caused by mismatch in the test fixture and electromagnetic coupling in space. Therefore, its calibration accuracy is the lowest. This calibration method can be used when only S21 is tested and the test accuracy is not high.

In PCB and other non coaxial structures, it is sometimes necessary to test the characteristics of wiring, vias, connectors, etc. In this case, the test instrument supplier does not provide standard calibration parts, and it is difficult for testers to make good calibration parts such as open circuit, short circuit and matching load at the test calibration port. Therefore, traditional sol calibration cannot be done. The advantage of TRL calibration is that there is no need for standard calibration parts, and the test calibration port can be extended to the required position. At present, TRL calibration has been widely used in PCB structure test.

Sol is generally considered as a standard calibration method. There are 12 calibration error parameters in the calibration model. Various errors are calibrated and calculated by using short circuit, open circuit, load and through. Since test instrument suppliers usually only provide coaxial calibration parts, sol calibration method cannot be used in non coaxial structures.

The above three calibration methods can be analyzed in detail by means of signal flow diagram, in which each error parameter has corresponding parameters in the signal flow diagram. Through the signal flow diagram, we can clearly understand the error sensitivity of various calibration methods, so as to understand the error range of the actual test. It should be pointed out that even the standard sol calibration method ignores five error parameters in the calibration model. Generally, these five error parameters will not affect the calibration accuracy. However, if you do not pay attention to the design of the calibration fixture during use, it will be impossible to calibrate.

A standard source is provided inside the spectrum analyzer for calibration. During calibration, only the internal standard source needs to be connected to the input port through the test fixture. The calibration time is about 10 minutes. The calibration of oscilloscope is simpler. Connect the probe to the internal standard source and confirm it. The calibration time is about 1 minute.

Testing and modeling of passive components

With the continuous increase of signal rate, passive components play a more and more important role in signal link. The accuracy of system performance simulation analysis often depends on the model accuracy of passive components. Therefore, the testing and modeling of passive components has gradually become an important part of PCB interconnection design of various equipment suppliers. Common passive components are as follows:

1. Connector

2. PCB routing and vias

3. Capacitance

4. Inductance (magnetic bead)

In the high-speed signal integrity design, the connector has the greatest impact on the signal link. For the frequently used high-speed connector, the common practice is to make the calibration fixture according to the TRL calibration method, and test and model the connector for simulation analysis. The test modeling method of PCB routing and vias is similar to that of connectors. TRL calibration is also used to move the test port to the required position, and then test modeling.

Capacitance model is used in signal integrity analysis, and it is mainly used in power integrity analysis. The commonly used capacitance modeling instruments in the industry are impedance analyzer and network analyzer, which are respectively applicable to different frequency bands. Impedance analyzer is applicable to low frequency band and network analyzer is applicable to high frequency band. If the network analyzer is used for power integrity test in the specific actual test, it is recommended to use the network analyzer in the whole frequency band of capacitance modeling to ensure the consistency of modeling and application. Because the impedance of capacitance is small, parallel connection is usually used when modeling with network analyzer. At present, the problem that has not been solved in capacitance modeling in the industry is how to eliminate the mutual coupling between fixture and capacitance in order to reduce the impact of fixture on modeling results.

In traditional power supply design, inductance (magnetic bead) is often used to isolate the power supply to reduce noise interference. In the actual design, the isolation inductance (magnetic bead) is often removed, and the power ground noise is reduced. This is because the inductance (magnetic bead) resonates with other filter elements. In order to avoid this situation, it is necessary to model and simulate the inductance (magnetic bead) to avoid resonance. The commonly used inductance (magnetic bead) modeling method in the industry also adopts the network analyzer. The specific method is similar to the capacitance modeling. The difference is that the inductance (magnetic bead) modeling adopts the series mode and the capacitance modeling adopts the parallel mode.

The modeling of the above passive components is mainly used in signal integrity and power integrity. In recent years, the simulation analysis of EMI is gradually developing, and the test modeling of EMI passive components has gradually become the focus of PCB interconnection design.

Power integrity test

With the continuous increase of chip power and the continuous decrease of working voltage, power ground noise has gradually become the object of attention in PCB interconnection design. From the perspective of test object, power integrity test can be divided into two steps: power system characteristic test and power ground noise test. The former is to test the performance of the power supply part of the system (passive test), the latter is to directly test the power ground noise (active test) when the system is working, and the synchronous switching noise can also be classified as power ground noise.

When testing the performance of the power supply system, the network analyzer is usually used, and the test objects are self impedance and transfer impedance of the power supply system. In general, the impedance of the power supply system is far less than that of the network analyzer system (50 ohms), so only through calibration can be done during the test. The impedance of the power supply system can be obtained by using the formula S21 = Z / 25.

Spectrum analyzer and oscilloscope can be used to test the ground noise of power supply. The input port of spectrum analyzer cannot access DC component. Therefore, DC blocking must be connected in series in the test fixture when testing the ground noise of power supply. The input impedance of the spectrum analyzer is 50 ohms, and the impedance of the power supply ground network is generally in the milliohm level. Therefore, the test fixture will not affect the system to be tested. The input impedance of the oscilloscope changes with different settings. Taking tds784 of tech company as an example, its low-frequency cut-off frequency changes with the change of coupling mode and system impedance.

All the methods described above are to test the power ground noise on the single board, and what really affects the operation of the chip is the power ground noise in the chip. At this time, it is necessary to determine the power ground noise in the chip with the help of synchronous switching noise test. Set the chip to have n IO ports, keep one of them static, and flip the other N-1 at the same time to test the signal waveform on the static network, that is, synchronous switching noise. The synchronous switching noise includes both power ground noise and crosstalk between different signals in the package. At present, there is no way to completely distinguish them.

Clock Jitter Test

In some high-end products, jitter has gradually become an important indicator affecting product performance. Here, we only briefly introduce how to use spectrum analyzer to test clock signal jitter and problem location, and the jitter test of data signal is not involved temporarily.

In most systems, the clock is generated by crystal oscillator or phase-locked loop. The jitter test of clock signal is relatively simple. It does not need high-end test instruments. The problem can be located by using common spectrum analyzer. The spectrum of the ideal clock signal is a clean discrete spectrum, which has a component only in the frequency doubling of the clock frequency. If the clock signal jitters, side lobes will appear near these frequency doubling, and the jitter is directly proportional to the power of these side lobes.

The specific method of using the spectrum analyzer to test the clock jitter is to find a testable point on the clock signal link, connect the point signal to the spectrum analyzer through DC blocking, and observe the test results. Since the test fixture is a linear system, there is no need to worry about generating new spectral components. The clock mentioned above is generated by crystal oscillator or phase-locked loop. In this case, the important reason for introducing clock jitter is the power noise of crystal oscillator or phase-locked loop. By comparing the power noise of crystal oscillator or PLL measured by the method described above with the side lobe in the clock spectrum, we can basically determine the cause of clock jitter. The solution to the problem is to redesign the filter circuit of crystal oscillator or phase-locked loop according to the clock spectrum sidelobe. In general, these problems can be solved by reasonably selecting the filter capacitor.

Technical direction of designcon 2005

Designcon is the first conference in the field of interconnection technology every year. At the annual conference this year, designcon 2005 mainly has the following technical development trends:

1. Simple simulation and test of power integrity has been widely used in the industry and is no longer a difficulty in analysis.

2. The modeling of capacitance and inductance (magnetic beads) has been popularized in the industry, and its method has been relatively perfect.

3. The focus of PCB interconnection design moves to packaging. Board level analysis has been relatively mature. The simulation and test of synchronous switching noise has gradually become a concern in the industry.

4. Jitter Test methods and standards have gradually become a concern of the industry. At the conference, many test equipment suppliers launched their own jitter analyzer.


This paper briefly introduces the test objects and test methods in the field of PCB interconnection design. With the continuous improvement of signal rate, some new test contents gradually appear, including power ground noise, passive device modeling, jitter and so on. According to his own work experience, the author puts forward the test methods for these new test contents. In the traditional signal waveform test, the length of ground wire should be reduced to avoid pigtail coupling noise and reduce the test accuracy. In the future PCB interconnection design, due to the increase of signal working frequency, the focus will be transferred to chip packaging, and the related testing and modeling technology will become the focus.

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