The communication principle of SPI is very simple. It works in the master-slave mode. This mode usually has one master device and one or more slave devices. It requires at least 4 wires. In fact, 3 wires are also OK (in one-way transmission). It is also common to all SPI based devices. They are SDI (data input), SDO (data output), SCK (clock), CS (chip selection).

(1) SDO – master device data output, slave device data input

(2) SDI – master device data input, slave device data output

(3) SCLK – clock signal generated by the master equipment

(4) CS – slave enable signal, controlled by master

Analysis of communication principle of SPI bus protocol


CS controls whether the chip is selected, that is, the operation of this chip is effective only when the chip selection signal is a predetermined enable signal (high potential or low potential). This makes it possible to connect multiple SPI devices on the same bus.

Next, there are three lines responsible for communication. Communication is completed through data exchange. First, we should know that SPI is a serial communication protocol, that is, data is transmitted bit by bit. This is the reason for the existence of SCK clock line. SCK provides clock pulse, and SDI and SDO complete data transmission based on this pulse. The data is output through the SDO line. The data changes at the rising or falling edge of the clock and is read at the next falling or rising edge. To complete one bit data transmission, the same principle is used for input. In this way, the transmission of 8-bit data can be completed after at least 8 changes of the clock signal (one for the upper edge and one for the lower edge).

It should be noted that the SCK signal line is only controlled by the master device, and the slave device cannot control the signal line. Similarly, in an SPI based device, there is at least one master device. Characteristics of such transmission: this transmission mode has an advantage. Different from ordinary serial communication, ordinary serial communication continuously transmits at least 8 bits of data at a time, while SPI allows data to be transmitted bit by bit or even suspended, because the SCK clock line is controlled by the master equipment. When there is no clock jump, the slave equipment does not collect or transmit data. In other words, the master device can complete the control of communication through the control of SCK clock line. SPI is also a data exchange protocol: because the data input and output lines of SPI are independent, it is allowed to complete data input and output at the same time. The implementation methods of different SPI devices are different, mainly due to the different time of data change and acquisition. There are different definitions for the acquisition of the upper or lower edge of the clock signal. Please refer to the documents of relevant devices for details.

In point-to-point communication, SPI interface does not need addressing operation, and it is full duplex communication, which is simple and efficient. In a system with multiple slaves, each slave needs an independent enable signal, which is slightly more complex in hardware than I2C system.

Finally, one disadvantage of SPI interface is that there is no specified flow control and no response mechanism to confirm whether data is received.

The SPI interface of AT91RM9200 is mainly composed of four pins: spiclk, MoSi, miso and / SS. Spiclk is the common clock of the whole SPI bus. MoSi and miso are the input and output flags of the master and the slave. MoSi is the output of the master, the input of the slave, and miso is the input of the master and the output of the slave/ SS is the flag pin of the slave. In the devices of two SPI buses communicating with each other, the slave is the one with low level of / SS pin, on the contrary, the host is the one with high level of / SS pin. In an SPI communication system, there must be a host. SPI bus can be configured as single master and single slave, single master and multiple slaves, which are master-slave to each other.

The chip selection of SPI can be expanded to select 16 peripherals. At this time, PCS output = NPCs, saying that npcs0 ~ 3 is connected to 4-16 decoder. This decoder needs to be connected to 4-16 decoder. The input of decoder is npcs0 ~ 3, and the output is used for the selection of 16 peripherals.

SPI protocol example

SPI is a ring bus structure, which is composed of SS (CS), SCK, SDI and SDO. Its timing is actually very simple. It is mainly the data exchange between two bidirectional shift registers under the control of SCK.

Suppose that the following 8-bit register is loaded with data 10101010 to be sent, and the rising edge is sent, the falling edge is received, and the high bit is sent first.

Then when the first rising edge comes, the data will be SDO = 1; Register = 0101010x. When the falling edge arrives, the level on SDI will be stored in the register. Then the register = 0101010sdi. In this way, after 8 clock pulses, the contents of the two registers will be exchanged with each other. This completes an SPI sequence in the.

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