1. How to build your own component library?

After creating a new project, the first step to draw a schematic diagram is to create the library you need, and the tool used is part developer. First, create a directory (such as mylib) to store the component library, and then open cds.lib with WordPad. The definition is: define mylib D: (board) mylib (the path of the directory). So you build your own library. In concept_ HDL component – add, click search stack to add to the library.

Analysis of common problems in cadence layout and wiring

2. The difference between save view and save all view, and between selecting change directory and not?

When building a component library, you should first save it, and select Save as far as possible

view。 In concept HDL, we can directly click on the device with the left mouse button to modify the external dimension of the device. At this time, if you enter the part again

After developer makes some modifications, if you select save all view, it will return to the original dimensions and select Save view

The modified shape will be retained.

3. How to build a part library and change the position of pin in symbol?

In project manager, tools / part developer can be used to create, select library, define part name, and add in symbol

Symbol, add package / addpin in package, enter pin in turn:

In package:

a. Name: pin’s logical name cannot be repeated

b. Pin: the label of the pin, the corresponding label after the back annotate in the schematic diagram

c. Pin type: the type of pin (input, output, etc., can be ignored temporarily)

d. Active: the trigger type of pin is high (high level), low (low level)

e. NC: fill in the label of the empty foot

f. Total: the number of all pins of this type

g. The following is omitted

In symbol:

a. Logical name: corresponding to the name in the package

b. Type: corresponding to the type in the package

c. Position: pin position in the device (left, right, top, bottom)

d. Pintext: the name of the pin displayed in the device (corresponding to the pin in the package, but can be repeated, such as in the package)

GND1 and gnd2 of can be set as GND)

e. Active: corresponding to active in package

Modify: open the device to be modified with part developer and * select Edit / restrict

Changes (if not selected, the device will be protected and the modified disk will be invalid)

a. Label and name of corresponding pin in package

b. The active type of pin

c. The order of pin pins in symbol (the order of pin pins will be changed when they are opened again after being saved for the first time

Pin devices, such as 232pins, are complicated to modify, so we try our best to ensure the one-time success rate. The order of pin pin in the device is determined according to the order in symbol, so the order of pin pin in symbol must be correct. If there is any error, you need to modify it. Select pin and press Ctrl key with up and down keys to move the pin position.

4. Why do save and package errors occur when drawing electrical schematic diagram?

When saving, the main reason may be: the drawn signal line may coincide with the pin of the component, or the signal line itself may coincide; The signal line is named repeatedly; The signal line may not be named; In the higher version (version 14.0 or above), the library you create cannot have the same name as the system itself; The number of pins in the original package is different from that in the original library. The reason for the error in packaging may be that the package type does not match the component (such as the number of pin pins, package type name, etc.).

5. How to modify device properties and package type in electrical schematic diagram?

Select attribute in the menu text drop-down menu, and then click device to open an attribute window. Click Add button to add name, value, JEDEC_ Type, etc.

6. How to define pad / via in pad design? And how to call *. Pad?

In pad design, when creating a pad, select the single type as the type. You should define the dimensions of the following layers: begin layer (sometimes end layer), soldermask and pastemask. When creating via, type generally selects through to define the size of drill hole, all layer layers (note the definition of thermal relief and anti pad) and soldermask. Generally, pastemask is the same size as regular, soldmask is several mil larger than layer, while thermal

The size of relief and anti pad is more than 10 mil larger than that of regular pad.

7. What should we pay attention to when making package library?

For encapsulation, you can use either file – > New – > package symbol in Allegro or wizard function. In this process, the key is to determine the distance between pad and pad (including the adjacent and corresponding pad), so as to ensure that the pin pin of the component can be completely pasted on the pad without deviation in the later packaging process. If you only know the size of pin, the pad size should be slightly larger than pin, generally 1.2-1.5 times larger in width and about 0.45mm in length. In addition to the pad size, you need to add some layers, such as silkscreen_ Top and bottom, because in the future when making light drawing documents (golden finger can not be used), ref DES is also best marked on the silkscreen layer. At the same time, pay attention not to draw the silk screen layer on the pad. It should also mark the position of pin 1. There are some special packages, such as golden finger. You can also add a layer of via keep out, or route keep out, etc. These can be added according to your own requirements. Note that after the encapsulation is completed, you must not forget to click Create symbol, otherwise the *. PSM file is not generated and cannot be called in allegro.

8. Why can’t I import netlist?

In Allegro, select import logic from the file option, and HDL concept from the import logic type. Note that in the import from column, confirm that it is the packaged directory in the working path. The system may automatically default to the physical directory.

9. How to define your own shortcut key in Allegro?

In the blank box below Allegro, next to the command prompt, type alias F4 (shortcut key) room out (command). Or there is an env file in cadence installation directory / share / PCB / text. Open it with WordPad, find the part defined by alias, and modify it manually.

10. How to define stacking? How to change the stack setting after wiring?

In Allegro, select setup –  cross section. If you want to add a layer, select Insert in the edit column, delete del, material model, FR-4 as insulation layer, copper as etch layer, layer type, conductor as wiring layer, plane as copper layer, dielectric as insulation layer, top, GND, S1, S2, VCC and bottom as etch subclass name.


Generally, positive is selected for type and negative is selected for plane layer. If it is found that the stack setting needs to be changed after wiring. For example, the original setting of 3 and 4 layers is the plane layer. Now it needs to be changed to 2 and 5 layers. It can’t be changed simply by renaming. You can first add two plane layers at 2 and 5 layers, and then delete the original plane layer.

11. Why are the components not displayed in the list or not displayed in the Allegro layout?

First, determine whether the path of psmpath and padpath is set. If not, you can set it in partdevelopment or manually add it in Env file. It is also possible that the device exists in the list, but it cannot be called out. Check whether the *. PAD file and package library file *. DRA, *. PSM used by the device exist in your working directory ×××/ Physical. Another possibility is that the page is too small to display devices and can be adjusted in setup- draw size.

12. Why is the device position inaccurate and the offset too large?

It is mainly due to the problem of grid setting. In setup grids, the spacing interval of X and y of each layer’s etch and non etch grids can be reduced. For some devices with strict position requirements, such as slots, gold fingers and other components used for interface, they should be positioned in the command line with coordinate instructions in strict accordance with the position size given by the designer. For example: X 1200 3000.

13. How to make a mechanical symbol and how to call it?

Select File –  new in Allegro, and select mechanical symbol in drawing type. The main purpose is to generate the frame model of PCB board. Although pad can be added here, there is no corresponding relationship between pins. Mechanical symbol

When finished, generate the *. DRA file. When calling in Allgro, select by symbol – Mechanical. Note the tick in front of Library in the lower right corner.

14. How to get a sorted Library of all components after layout?

If you want to delete some useless files, or only one *. BRD file, and want to get all the information of components and pad packaging library, you can use this method: save *. BRD in a new directory, select export libraries in file -, click all the options, and then export, You can generate all *. Pad, *. PSM, *. DRA files in your new directory.

15. How to define the rule of distance between lines?

For example, we define the distance between CLK line and other signal lines

In Allegro: setup constraints, set values in spacing rule set. First, add a constraint set name. For example, we call it clock_ Net, and then define the specific rules to be followed below.

For example, line to line is defined as 10 mil. Next, select properties from the edit menu in the Allegro main window to jump out of your control toolbar, select net from find by name, and click more in the lower right corner. Select the CLK line you want to specify in the list of the new pop-up window, such as CK0, CK1, CK2, etc. confirm the selected objects on the right to select all the lines and click apply. A new window will appear. Select net from available properties on the left_ SPACING_ Type, assign a value to it on the left (name optional), such as CLK. Back to setup constraints,

Just now, under set values, click the assignment table to assign the defined rules to the selected net.

In specctra, you can first select the signal line (select nets by list) to define the spacing, and then select selected net clearance in rules. In this window, you can define a series of wiring rules. For example, to define the spacing between lines, you can define it in the wire wire column. Note that when you click apply or OK, the column still displays – 1 (meaning unlimited), Just look at the blank bar at the bottom of the screen to see if there is a defined message prompt.

16. Why can’t you draw a line in Allegro at a 45 degree angle?

In the line lock of the control bar, you can change 90 to 45. If you want to draw an arc, you can change line to arc.

17. How to define the maximum and minimum routing distance in CCT?

Similar to the above method of defining spacing, after selecting the line to be defined and rules – > < selected Net – > < timing, you can define the maximum and minimum length limit of routing in minimum length and maximum length, or use time delay as the limit. Another method is to extract the extension structure of a signal line in specctra quest as a model, define the length limit of each section of wire in it, and then generate a rule file to constrain the routing of the same type of signal line.

18. How to save and read disks (color setting, rule saving) in CCT?

In specctra, you can save the current wiring with file – < write – < session, save the rule files with file – < write – < rules did files, use file – < execute do file when calling, and then type the file to be called, such as initial.session or rules.rul. Use write colormap and load colormap in color palette to save and read color settings.

19. How to define the position of automatic drilling, how to drill a row of through holes and define their arrangement shape in CCT?

CCT has the function of automatic drilling, in autoroute -, pre route -, fanout. You can specify the direction of the vias. For example, if you want to place all the vias inside the pad, you can select inside in location. Some other restrictions can also be defined. In addition, sometimes we can select a group of lines for parallel routing. At this time, we may punch a row of vias at the same time. Right click the mouse and select set via pattern to select its arrangement shape. There are also shortcut buttons at the bottom right of the window.

20. Why does the maximum and minimum distance of the prompt not change with the length of the route?

After defining the rules of the longest and shortest routing, we will have a digital display during the routing, which will tell you how much deviation from the defined rules if you follow the current routing. Generally, those within the regular length will be displayed in green font, while those exceeding or insufficient in length will be displayed in red font, and + / – will be used to prompt the deviation. However, the deviation of this prompt does not simply vary with the length of your line. It is based on your routing direction, the software automatically calculates the comparison between the routing length in this direction and the specified length. If you change the routing direction, it will also recalculate.

21. How to lay the plane layer? How to modify after paving?

Copper laying must be carried out in Allegro, add -, shapes -, solid fill. At the same time, in the control toolbar, select etch for active class and select the plane layer to be laid for subclass, such as VCC or GND. Then you can draw the frame, pay attention to the distance from the outline is about 20 mil. After done, you will enter the copper laying operation interface, and select Edit – “change net (by name) to name the plane layer. In shape parameters, determine whether anti pad and thermal relief are used, and then select void auto. The software will automatically detect the thermal relief. After completion, there will be a log report. If there are no errors, you can lay the shape and fill it. If the copper needs to be laid again due to the change of vias after laying, you should select Edit – shape, click on the shape, and then right-click to select done. In this way, the thermal relief connected to the shape will be automatically deleted. You can’t delete the copper laying shape layer, otherwise the thermal relief will be left on the plane layer.

22. How to define the line width between vias and shapes in thermal relief?

In the set standard values of Allegro’s setup – constraints, the width of each layer can be defined. For example, the line width of VCC and GND can be defined as 10 mil. When laying copper, pay attention to whether some line width definitions in shape – “parameters are set to DRC value.

23. How to optimize the routing without changing the overall shape of the routing?

After the completion of the wiring, it needs to be optimized, generally using the system automatic optimization, mainly to change the right angle to 45 degrees, and the smoothness of the line. In the list that appears, select line smoothing and perform gloss. But sometimes, in order to ensure the same routing distance, deliberately walk into some curved lines. During optimization, click the box on the left side of line smoothing and select only convert 90’s to 45’s to remove all other checks, In this way, it will not straighten or deform the designer’s intentionally bent routing.

24. How to add teardrop pads and how to delete them?

In the optimized parameters option, only select the penultimate, pad and T connection filler, and remove the pin option to optimize. If you want to delete it, just select dangling in line smoothing

Lines. Note: if there are no special requirements, we will not do this optimization now.

25. What should be done if the package library needs to be changed after wiring?

After the device is placed, if the package library is changed, place – “update symbols” can be used. If the pad is changed, check before update symbol padstacks. After the completion of wiring, try to avoid the change of the encapsulation library, because if the update, the connection on the pin will move with the symbol, resulting in the loss of many connections, and the specific solution remains to be studied.

26. Why can’t *. BRD be saved?

In this case, pay attention to the prompt in the blank column at the bottom of the screen. It may be that there is not enough space on the hard disk. Another possibility is that there is an error in the database, and the software will automatically save it as a *. Sav file. At this time, you can re-enter cadence (you may need to restart), open *. Sav, and then save it as *. BRD. Or run dbfix. Sav under DOS, it will be automatically converted to *. BRD file, and then it can be called.

27. What are Allegro’s database correction commands under DOS?

Sometimes Allegro will have some illegal over operation, resulting in some data errors. We can run some correction commands in DOS mode under the working directory (physical directory), such as dbcheck

*. BRD, or dbfix *. BRD. In practice, however, these commands seem to have little effect.

28. How to generate *. DML model library?

In DOS mode, under the working directory, type the brd2dmml *. BRD command, so that the model library DML file corresponding to BRD file will be generated in this directory.

29. How to use IBIS model to simulate in specctra quest?

Firstly, the IBIS model is transformed into a *. DML file. In specctra quest Si expert, analyze – Si / EMI Si – library, in the lower right corner of the new window, click translate – ibis2signature, and then select *. IBS file in browse to convert it into *. DML file. Then load all devices into corresponding models in analyze – Si / EMI Si – model assign. Then we can use probe to extract signal lines for simulation.

30. What files are needed to generate Gerber file? How to produce?

After the completion of PCB wiring, the last task is to generate the optical drawing file required by the manufacturer, and the specific steps are completed under the Allegro tool. Under the manufacturing menu, click the art option, and an art control form window will appear. In addition to the generated top, GND, S1, S2, VCC and bottom 6 layers, the provided photo files should also include silkscreen_ top, silkscreen_ botom, soldermask_ top, soldermask_ bottom, pastemask_ top, pastemask_ Bottom, drill drawing file, and drill hole. Let’s take the top layer of silkscreen as an example.

1) In the Allegro window, click the color icon. In the generated window, global visibility selects all invisibility to turn off all displays.

2) In group, select geometry. Then select all subclasses (boards)_ Silkscreen under geometry, package geometry_ top 。

3) Also select autosilk in group / manufacture_ top 。 Select silkscreen in group / components, subclass ref des.

4) Select the OK button, and silksscreen will appear in the Allegro window_ Top layer.

5) In the work control form window, right-click bottom, select add from the drop-down menu, and then enter: silkscreen in the window that appears_ Top, click O.K, and a new silkscreen appears in avilibity films_ top。

Note: select use aperture rotation in film option, and fill in 5 (or 10) in the underlying line width to define the width of the line without line width.

Follow the steps above to generate the silkscreen_ Bottom layer. soldermask_ Top and soldermask_ The bottom layer is in gemoetry group and stack up group (select pin and via subset); Pastemask_ Top and pastemask_ The bottom was in the stack up group (pin and via subsets were selected); Drilldraw includes outline, dimension in group / board geometry and ncdrill in manufacturing_ Legend。 In this way, the above layers are added according to the above steps. Then in the artwork control form window, click Select all to select all layers, and then click apertures. Button, a new window editaperture wheels will appear. Click Edit, click Auto in the new window, and select with rotation to automatically generate some aperture files. Then click O.K. In the art control form, click create art to generate 13 art files. Go back to Allegro window, click drill tape menu in NC option under manufacture menu to generate a *. Tap file. So far, all 14 photo files are generated.

31. How to adjust the light drawing file? And how to make the plane layer light drawing file of negtive?

Create a new blank layout file, file import artwork, and then select *. Art file in browse and Gerber 6 in manual × 00。 Don’t click OK. Click load file. When calling soldermask, check before display pad targets. When calling the silksscreen layer, you may find that there is no device name flag. This is because the width of the underlying line width is not defined when the photo file is made on it, but when the package library is made in the past, the silk_ If the ref marked in the screen layer has no width defined, it will not be displayed when it is called. In addition, if you want to make the light drawing file of negtive. When making photo files, the plot mode of GND and VCC layers should be negative.

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