Cost is an important factor to consider when developing system for mass application. There are several aspects that affect the total cost of ownership, not just the price of each component. This includes the power requirements of silicon wafers, the total cost of materials (BOM), and the efficiency of engineers designing and testing systems. It is very important to select FPGA supplier, and all aspects that affect system cost should be considered, which is reflected in the whole product design cycle.

Altera cyclone V FPGA helps designers reduce the total cost of the system in a variety of ways. In addition to the powerful design tools provided by Altera (tslp-28 nm) system architecture, Altera can also benefit from the low power consumption tools provided by Altera. With cyclone V FPGA, users not only achieve the lowest total cost of ownership in the industry, but also get the most complete range of low-cost devices from 25K logic unit (LE) to 301k Le, and the only 28 nm solution of less than 100k le.


Reduce the power consumption and increase the efficiency of your products. These difficult problems are what design engineers must face at present. Fortunately, Altera’s 28 nm series offers customized solutions to these problems.

Using TSMC’s 28lp process and wire bonding packaging, cyclone V FPGA achieves unprecedented performance, low system cost and minimum power consumption among all 28 nm FPGAs. There are six target models for the cyclone V FPGA family: logic only (E) model, 3G transceiver based (GX) model, 5g transceiver based (GT) model, and SOC derivatives of these models (i.e., Se, SX and St respectively), each of which contains an integrated dual core arm? Cortex? -A9 MPCore? Application level processor. Each device model integrates a wealth of hard core intellectual property (IP) modules to help you highlight product advantages and win over more with less. Compared with previous generation architectures, the advanced technologies adopted include adaptive logic module (ALM), precision adjustable digital signal processing (DSP), segmented phase locked loop (FPLL), hard core memory controller, etc., which are just a few examples.

Compared with the previous Altera device family and competing 28 nm FPGAs, your cyclone V FPGA can significantly reduce your total cost of ownership. The cost advantage is derived from TSMC’s 28lp manufacturing process, the rich architecture features of devices, and Altera’s various high-efficiency design tools. Cyclone V FPGA is the best choice for all kinds of market applications, including industry, communication, military and automobile.

Using TSMC 28lp manufacturing process to reduce design cost

Altera adopts a two pronged manufacturing strategy at 28 nm. For systems that need to increase bandwidth as much as possible, the 28 nm high performance (28hp) process of TSMC is used, and the 28lp process is used for low-cost and low-power applications. Stratix? V FPGA adopts 28hp technology, while the aria? V FPGA adopts 28hp technology? Both V and cyclone V FPGA adopt LP technology. For any electronic system, reducing power consumption certainly means reducing operating costs and total cost of ownership.

According to different process granularity, users can choose the most suitable product to meet their needs. TSMC is Altera’s OEM line partner, and the company believes that “by adopting solutions on multi technology platforms, users can better play their advantages of flexibility and launch products with the best performance.” Compared with the “meet all requirements” approach used in competing 28 nm products, providing multiple products is more suitable for users. Using a manufacturing process, it is not easy to optimize at the same time to achieve low power consumption and high performance. Even the most purposeful classification strategy can not solve the dilemma that single process power consumption classification will have adverse impact on performance and performance classification will have adverse impact on power consumption. Moreover, for users, the hierarchical strategy may increase the system cost and bring obvious planning and supply risks.

On the contrary, the cost optimal 28lp process customization used in cyclone V FPGA meets the requirements of low-cost and low-power applications. By using a variety of technologies, including using longer gate channels than the 28hp process, it reduces both leakage current and dynamic current. The cost is further reduced by using more traditional metal processes than 28hp and wire bonding packaging technology. Compared with flip chip packages, wire bonded packages save users about $5 per model. Altera’s transceiver design expertise is reflected in the high reliability and low power consumption of the high-speed serial interface. In the early power estimation benchmark, compared with the cyclone IV FPGA, the cyclone V FPGA showed a significant advantage in low power consumption (Figure 1), and the total power consumption was 40% lower than that of Xilinx artix-7 FPGA (Figure 2).

Altera cyclone V FPGA device can reduce the design system cost and power consumption

Altera cyclone V FPGA device can reduce the design system cost and power consumption

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Altera’s full range of low-cost 28 nm products increase design flexibility

From the point of view of system design, a FPGA family has great advantages in providing a variety of device density choices. The capacity of cyclone V FPGA ranges from 25K le to 301k Le, which has obvious advantages in the low-cost 28 nm device market. In this way, designers can design on smaller models, and if the product range is expanded, it can be transplanted later. Similarly, if the design is smaller, they can use smaller devices. Generally speaking, if the device family is changed in the middle of the design cycle to deal with such engineering changes (ECO), the time and resource costs are very high. Cyclone V series has a wide range of vertical porting options. Altera provides the most comprehensive and cost-effective low-cost FPGA devices.

Altera cyclone V FPGA device can reduce the design system cost and power consumption

Cyclone V FPGA architecture reduces design cost

Altera’s 28 nm architecture reduces design costs in a variety of ways. The core architecture improves the logic efficiency and is the highest density interconnection structure at present. Hard core IP achieves high performance, improves flexibility and shortens design time. The optimized transceiver has the best signal integrity of the same kind and reduces the debugging time. Only two voltage rails are used, so the power distribution network is cheaper and easier to design. Using FPLL, it can synthesize any frequency clock without expensive oscillator. The intelligent pin layout improves the wiring ability and signal integrity of the device.

Core architecture and cabling improve logic efficiency

Cyclone V FPGA adopts innovative core architecture to realize logic and DSP functions efficiently. It is estimated that, compared with previous generations of technologies, the enhancement of the kernel alone can save designers $20 per model due to increased logical utilization.

The basic building block of cyclone V architecture is ALM. It includes an 8-Input segmented look-up table (LUT) and two adders and four registers – all tightly packed together to improve performance and make good use of silicon area. Similar to Altera’s high-end devices, this architecture is the inheritance and development of cyclone IV FPGA. Its basic building module is le, with 4-input LUT and a register. The combination of ALM and compact package not only improves the cost performance of silicon chip, but also makes it easier to achieve timing convergence, especially requiring a large number of registers and pipelined designs. The cyclone V series provides equivalent 301k-le in the form of vertical proximity logical array modules (Lab), each lab has 10 alms. The ALM is automatically configured by the adapter (by Altera’s quartus? II development software), to achieve the pure combination or arithmetic functions required by the application.

Altera cyclone V FPGA device can reduce the design system cost and power consumption

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Cyclone V FPGA has a new embedded memory module, namely, m10k. The size of the memory module is smaller than that of the embedded memory module in the competitive architecture, so the granularity is improved. More memory ports are provided per unit silicon chip area, and few modules are wasted. The on-chip memory architecture is very suitable for applications that require a lot of DSP, such as motor control, studio equipment and 3D TV. In order to process the buffer and delay cells efficiently and cost effectively, the cyclone V device also provides a smaller 640 bit mlab module.

Cyclone V FPGA also uses high performance and precision adjustable DSP module. Using Altera’s innovative DSP module, as well as the FIR filter’s dedicated coefficient block and feedback path, the designer can independently configure the accuracy of each multiplier from 9×9 to 27×27 bits, depending on the application requirements. Through this function, cyclone V FPGA realizes the multiplier with appropriate precision required by designers in application, and supports designers to adopt the most efficient hardware as far as possible.

For example, a simple video processing application requires only 9 bits of precision, while some high-end color systems require 24 bits. For 9-bit video applications, a module can be divided into three 9-bit multipliers, which improves the efficiency of DSP module by three times. A precision adjustable module can efficiently meet all these range requirements. Thus, it supports designers to adapt FPGA resources to their algorithms rather than to the limited resource requirements.

Hard core IP achieves high performance, improves flexibility and shortens design time

Altera enhances some common IP modules (for example, double data rate memory controller, protocol stack, even embedded ARM processor) in fixed silicon chip, releasing valuable programmable logic resources for other logic functions, thus improving performance, reducing power consumption and cost. As an example, PCI Express? (PCIe?) The protocol stack needs about 150k le to be implemented as a soft core, and only one third of the device area is required in the hard core module. Users who try to implement the core of PCIe with competitive technology and tools will find that using Altera hard core IP and qsys system integration tools can save an average of 6 weeks in design and debugging time. This means significant cost reduction for the design team.

Altera also introduced the first kind of multi-functional support for PCIe in FPGA. This technology simplifies the sharing of the bandwidth between different peripherals. It supports eight functions, and the multi-function function of PCIe supports the integration of multiple single function endpoints into one multi-functional endpoint. This shortens the development time and saves 20K le.

With the multi-function of PCIe, designers can customize the industry standard processor and a variety of peripherals that reside in FPGA logic. Moreover, with the support of multi-function, designers can use standard operating system (OS) driver software to share the PCI link bandwidth on FPGA peripherals. When there is no multi-functional support, one of the main tasks in the development process is to customize the driver software to achieve this resource sharing function. Moreover, the multi-functional support does not need multiple soft core or hard core of the PCIe kernel, which is integrated into a multi-functional PCIe endpoint, thus effectively reducing the cost.

Hard core IP first appeared in Altera’s 40 nm devices, as a PHY layer unit, so there is no need for external high-performance serial I / O circuit board components. In altera 28 nm devices, the embedded hard core IP module realizes the cost, performance and power consumption characteristics of ASIC without sacrificing design flexibility. For example, you can configure the PCIe hard core IP module in the cyclone V GT device to support the PCIe GEN1 or Gen2. In addition, the cyclone V FPGA also provides two hard core PCIe cores – twice as many as competing devices. Compared with the soft core logic implementation, the power consumption of hard core IP module is reduced by 65%, while the performance is improved by 50%. Table 1 lists the hard core IP functions in cyclone V FPGA and the amount of resources saved by hard core implementation.

Altera cyclone V FPGA device can reduce the design system cost and power consumption

Mature and reliable transceiver, optimized for various data rates, shorten the debugging time

Altera’s 28 nm series products introduce modular transceivers to support designers to meet the device performance requirements of practical applications. In all of Altera’s 28 NMS FPGA families, this transceiver uses the same basic architecture, with maximum operating rates ranging from 3.125-gbps to 28 Gbps. Like Stratix V and arria V devices, cyclone V transceivers can dynamically switch between several different rate settings, and can slow down to reduce power consumption. This selection function provides a method to reduce the average power consumption of the system. When idle, the transceiver works at the minimum rate and switches to high-speed operation as required.

If applications such as I / O expansion only need 5-gbps or lower rate transceivers, the power consumption and cost of large transistors operating at 28 Gbps will not occur. On the contrary, the transceiver achieves 3.125-gbps and 5-gbps performance with the lowest power consumption and lowest cost, and the cyclone V FPGA family can adapt to the design well. Similar to the transceivers in Stratix V and aria V devices, cyclone V FPGA transceivers support a variety of protocols, including 3G SDI, Gigabit Ethernet (GBE), CPRI, display port, PCIe, serial ATA (SATA) and serial RapidIO? Etc. The integrity of Altera transceiver signal and the real-time debugging function realized by transceiver toolkit can save several weeks of PCB development and debugging time.

For more information about transceiver kits, please refer to the transceiver kits on Altera website《 》Page.

Only two kinds of voltage rails are used, which simplifies the power distribution and reduces the cost

Among all low-cost FPGAs, cyclone V FPGA requires the least number of voltage rails. They have built-in on-chip voltage regulators, so you only need to use two voltage rails to support both logic and transceiver power. In this way, the on-board voltage regulator is not needed, the wiring congestion is avoided, the number of circuit board layers required is reduced, and the circuit board design is simplified. Competing devices require at least three voltage rails to support core, I / O, and transceiver logic. Additional power rails require additional components and PCB area, and may cause wiring congestion problems, so the cost may increase by $10 to $30 in your board development budget.

FPLL can be synthesized at any frequency without additional oscillator

The general PLL of Altera 28 nm device is FPLL, which has the functions of advanced segmented frequency synthesis and M / N frequency realization. In standard PLL, m and N values are integers. Altera adopts delta sigma modulator, and uses 32-bit m and N values in the feedback path, and adopts segmented value to support feedback m-divider. This precise frequency synthesis function is supported. By synthesizing any clock frequency, FPLL can replace the oscillator on the circuit board, thus reducing the cost and area of the circuit board.

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The intelligent pin layout improves the wiring ability and shortens the debugging time

The cyclone V FPGA provides the best signal integrity at the lowest development cost. The conventional checkerboard power and ground modes are adopted to simplify the layout. In addition, the conventional transceiver layout is on the left side of the device and repeated, while the receiver is always external, thus achieving optimal signal integrity. The memory I / O pin should be placed away from the transceiver as far as possible, and shielded from the transceiver. Altera’s approach is to reduce the investment in the time-consuming debugging process by avoiding pin layout problems.

Altera system design tool reduces total cost of ownership

Altera’s integrated design environment, including Quartus II software, provides the most advanced tool set for FPGA industry, reduces development costs and shortens the time to market. With Quartus II software, you can design the whole FPGA quickly and efficiently from concept conception to product. It provides a timing convergence tool (timequest timing analyzer) similar to ASIC, and supports many debugging functions in the system. Its high performance features include qsys system integration tool, system controller, transceiver kit, DSP Builder and SOC virtual target software platform.

Using qsys to realize system integration

Qsys is the next generation of SOPC builder tool to help designers build and adjust the system. Qsys supports the rapid integration of user developed and commercial IP modules, speeding up your design process and improving efficiency. Moreover, qsys supports hierarchical design and simplifies the management of large-scale design. For example, it is easy to implement and test a system with hundreds of components, and can be managed to facilitate design reuse. Based on the chip network architecture and automatic pipeline, the performance of push-button interconnection is 2 times higher than that of SOPC builder. In the end, qsys helped designers shorten the development time of several months and implement cores such as PCIe in days rather than weeks.

Research and debug the system through the system console

Using the system console, users can use the system level session function to debug FPGA at a higher level by using script or interactive operation in the command line or GUI of the system console through the convenient and simple software application programming interface (API). The system console is very suitable for PCB development and other tasks. It enables designers to use and control FPGA hardware through JTAG or TCP / IP, thus saving several weeks.

DSP Builder with advanced module library is used to design DSP application

With DSP Builder, you can use matlab? The most famous DSP design tool in the world? Simulink? To design FPGA. With this design tool, you can continue to stay in your familiar EDA environment, design with easy to understand schematic input tools, and automatically generate comprehensive RTL code for target Altera FPGA. You can even compile the design in Quartus II software directly from MATLAB environment. You can develop FPGA design without learning Verilog or VHDL in advance. Compared with the input of individuals and FPGA design experts, seamless integration from engineering system level (ESL) design environment to FPGA design environment can save a lot of investment of design team.

DSP Builder provides two main plug-ins for Simulink: basic module library and advanced module library. It supports you to drag components, link them together, and conduct simulation. Both module libraries allow you to put integrable components into the Simulink schematic browser. Using advanced module library, DSP Builder will automatically pipeline your data path to meet your Fmax target requirements and reuse the module as much as possible.

SOC virtual target

Altera SOC FPGA virtual target is a fast functional simulation of dual core arm cortex-a9 Mpcore embedded processor development system in cyclone V SOC FPGA. This comprehensive prototype development tool “out of the box”, runs on PC, starts Linux operating system, and models the actual development circuit board. The virtual target is compatible with its simulated hardware binary and register, and supports the development of device specific product software. After obtaining the actual hardware, it can run in the hardware without modification. With virtual prototyping tools, you can start software development quickly before you have hardware, further improving the effectiveness and quality of software teams.

In order to fully represent Altera SOC FPGA devices, the virtual target also uses a PC based simulation FPGA extension function called loop FPGA. As shown in Figure 5, the extended loop FPGA supports the connection of virtual targets to Altera commercial FPGA development boards, on which you can implement your own custom IP to run with other components of the virtual target. With this feature, you can test your software with FPGA hardware such as custom peripherals and hardware accelerators.

Altera cyclone V FPGA device can reduce the design system cost and power consumption

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Integration example — Automobile analysis based on cyclone V FPGA

Cyclone V FPGA is suitable for many applications. One of the fast developing applications is automotive analysis. The low cost of ownership and powerful features of cyclone V FPGA are very suitable for this application field. In the process of serial video data processing, a lot of computation and a lot of memory are needed, which can make use of the hardware characteristics of hard core memory controller, high-speed serial transceiver, FPLL and rich internal logic and memory resources.

In addition, users can easily develop complex video processing systems in qsys by using Altera’s video and image processing (VIP) package. Figure 6 shows an example of video data integration in a car. In this environment, cyclone V FPGA can be used efficiently because it provides high definition functions and other video processing features, such as zoom and target detection, which is not only low cost but also low power consumption.

Altera cyclone V FPGA device can reduce the design system cost and power consumption


Cyclone V FPGA reduces total cost of ownership. TSMC’s 28lp process is designed to reduce power consumption as much as possible, and is also the lowest cost 28 nm manufacturing process. Low power consumption means that the system reliability of the user value chain is improved, the system life is prolonged, and the total operation cost is reduced. In addition, cyclone V FPGA has many architecture advantages, which can reduce the system cost, including hard core memory controller, efficient logic and wiring resources, FPLL, precision adjustable DSP module, and minimum voltage rail requirements. In addition, Quartus II software with qsys and system console functions, DSP Builder and SOC virtual target platform, supports you to design cyclone V FPGA efficiently and conveniently. For FPGA designers, Altera chips and design tools work together to achieve the lowest total cost of ownership.

Editor in charge: GT


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