While Total SoluTIon is gradually becoming a trend and the industry chain is shifting down, the field of EDA tools is also changing. EDA suppliers should pay more attention to the whole process of verification, manufacturing, etc. In reality, many EDA companies still focus on several tool modules, ignoring the consideration of the whole process.
In traditional EDA tools, one execution core is used to implement chip design, including analog design, digital design, mixed-signal design, and package design. Today, the advancement of IC technology and the needs of the 3C field drive the innovation of EDA tools. The design requirements of low power consumption, high integration, and emerging RF technologies, especially in China, the growth rate of the emerging 3C field is much higher than that of mature Market, customers in the 3C field put forward more demands for end-to-end solutions.
Therefore, it is not enough to have only point tools, and transition from providing point tools to supporting the whole process is the future development direction of EDA manufacturers. Optimizing the end-to-end process is the best idea, from architecture to energy-efficient design, throughout the entire process of design, placement and routing, and verification.
The expansion from the executive core to the upper and lower ends has become a new growth point in the EDA industry, and many EDA companies have begun to set foot in it. Extend upward to verification, including simulation and system hardware simulation, focusing on improving system architecture; downward is Design for Manufacturability (DFM), DFM emphasizes the concept of "Big Design", is a broader Design, each process module in DFM All have a self-test function and then transmit down.
Based on this concept, it is to connect various point tools such as analog, digital, mixed-signal and package design, and provide a functional verification platform and DFM technology to form a loop between design and manufacturing.
In digital IC design and PCB design, there are two major challenges: smaller area and lower power consumption. According to the requirements of design complexity and process nodes, it can be divided into three levels: X, XL and GXL. It is also a wise choice to provide EDA design solutions according to different needs of customers. At present, China's demand for L-class is mainly, and the demand for XL-class design has also begun to appear.
Power consumption is a focus of attention in the industry, and it is also a problem that needs to be solved collaboratively by upstream and downstream manufacturers in the industry chain. CPF (Common Power Format, Common Power Format) is one of the low-power formats that has attracted much attention nowadays. It emphasizes the idea of optimizing the entire process to achieve automatic low-power management. The Power Forward IniTIaTIve (PFI) Alliance was established by partners including EDA tools, IP, chips, systems, manufacturing and equipment manufacturers to jointly promote the standardization of CPF.
As a low-power common language, after CPF is translated into a common language, it needs to be integrated into the entire process. If the performance of an IP module is not good, the power consumption of the entire system may still be very high. Each module in the process will be self-tested, to avoid problems in the final inspection and to completely modify the design. Therefore, the self-test of a single IP module is the key to ensuring low power consumption in the entire process. After CPF passes the test next year, Cadence will apply CPF to all related tools.
Responsible editor: tzh