Author: Doug Mercer of ADI company, consultant researcher; Antonio miclaus, system application engineer

target

The purpose of this experiment is to study a simple NPN emitter follower, sometimes referred to as a common collector configuration.

Material Science

• Jumper
• A 2.2 K Ω resistor (RL)
• A small signal NPN Transistor (Q1 uses 2N3904)

explain

The bread board connection is shown in Figure 2. The output of any waveform generator W1 is connected to the base terminal of Q1. Oscilloscope input 1 + (single ended) is also connected to W1 output. The collector terminal is connected to the positive (VP) power supply. The emitter terminal is connected to the 2.2 K Ω load resistance and oscilloscope input 2 + (single ended). The other end of the load resistance is connected to the negative (VN) power supply. To measure the input-output error, connect 2 + to the base of Q1 and 2 – to the emitter to display the difference of oscilloscope channel 2.

Figure 1. Emitter follower

hardware setup

The waveform generator is configured as a 1 kHz sine wave with a peak to peak amplitude of 4 V and an offset of 0. The single ended input (2 +) of oscilloscope channel 2 is used to measure the voltage of the emitter. The oscilloscope is configured to connect channel 1 + to display the output of AWG generator. When measuring the input-output error, connect channel 2 of the oscilloscope to display the difference between 2 + and 2 -.

Figure 2. Emitter follower bread board circuit

Procedure steps

Configure the oscilloscope to capture multiple cycles of the measured two signals. The generated waveform is shown in Figure 3.

Figure 3. Emitter follower waveform

The ideal value of the incremental gain (Vout / VIN) of the emitter follower is 1, but it is always slightly less than 1. The gain is generally calculated by the following formula:

It can be seen from the formula that to obtain a gain close to 1, we can increase RL or decrease re. It can also be seen that re is a function of ie. when ie increases, re decreases. In addition, it can be seen from the circuit that IE is related to RL. If RL increases, ie will decrease. In a simple resistor loaded emitter follower, these two effects cancel each other out. Therefore, to optimize the gain of the follower, we need to find a method to reduce re or increase RL without affecting the other party. If the follower is viewed from another point of view, the difference between the input and output should be constant within the expected swing because of the DC offset of the transistor VBE itself. Affected by the simple resistive load RL, the emission collector current ie increases and decreases as the output swings up and down. Because VBE is an exponential function of IE, when the variation coefficient of IE is 2, the variation amplitude of VBE is about 18 MV (at room temperature). Taking the swing of + 2 V to – 2 V as an example, the minimum ie = 2 V / 2.2 K Ω or 0.91 Ma, and the maximum ie = 6 V / 2.2 K Ω or 2.7 ma. The variation amplitude of VBE is 28 MV. According to these experimental results, we can improve the emitter follower from one aspect. In order to keep the emitter current of the amplifier transistor constant, the current mirror in “adalm2000 experiment: BJT current mirror” is used to replace the emitter load resistance. The current mirror can obtain a relatively constant current in a wide voltage range. This relatively constant current in the transistor causes the VBE to be quite constant. From another point of view, the extremely high output resistance in the current source can effectively improve RL, but re remains at the low value set for the current.

Improved emitter follower

• A 3.2 K Ω resistor (connect 1 K Ω and 2.2 K Ω resistors in series)
• A small signal NPN Transistor (Q1 uses 2N3904)
• Two small signal NPN transistors (ssm2212 for Q2 and Q3) for optimal VBE matching

explain

The bread board connection is shown in Figure 4 and figure 5.

Figure 4. Improved emitter follower

hardware setup

The waveform generator is configured as a 100 Hz triangular wave with a peak to peak amplitude of 3 V and an offset of 0. The single ended input (2 +) of oscilloscope channel 2 is used to measure the voltage of the emitter of Q1. The oscilloscope is configured to connect channel 1 + to display the output of AWG generator. When measuring the input-output error, connect channel 2 of the oscilloscope to display the difference between 2 + and 2 -.

Figure 5. Improved emitter follower bread board circuit

Procedure steps

Configure the oscilloscope to capture multiple cycles of the measured two signals. The generated waveform is shown in Figure 6.

Figure 6. Improved emitter follower waveform

Figure 7. Excel chart example of input-output error of resistance and current source load

Low offset follower

The follower circuit we discussed earlier has a built-in offset – VBE. The circuit used next uses the VBE up offset of the PNP emitter follower to offset the VBE down offset of the NPN emitter follower.

Material Science

• A 6.8 K Ω resistor
• A 10 K Ω resistor
• One 0.01 μ F capacitance
• A small signal PNP transistor (Q1 uses 2N3906)
• Three small signal NPN transistors (2N3904 or ssm2212 for Q2, Q3 and Q4)

explain

The bread board connection is shown in Figures 8 and 9. The output of the function generator is connected to the base terminal of the PNP transistor Q1. The collector terminal of Q1 is connected to diode NPN Q3, which is the input of current mirror. The emitter terminal is connected to the base terminal of the resistor R1 and the NPN transistor Q2. Oscilloscope input 2 + is connected to the emitter of Q2 and the collector of Q4. The emission sets of Q3 and Q4 are connected to the negative (VN) power supply. For optimal transistor matching, Q3 and Q4 use ssm2212 NPN matching.

Figure 8. Low offset follower

hardware setup

The waveform generator is configured as a 1 kHz sine wave with a peak to peak amplitude of 4 V and an offset of 0. Oscilloscope input channel 2 is set to 500 MV / Div.

Figure 9. Bread board circuit of low offset follower

Procedure steps

Configure the oscilloscope to capture multiple cycles of the measured two signals. The generated waveform is shown in Figure 10.

Figure 10. Low offset follower waveform

A problem arises when a simple emitter follower drives a capacitive load. Because the emitter current is only affected by β Multiplied by the limit of the base current, which is provided by the signal source driving the base, so the rise time of the output is relatively fast. The descent time may be much slower and will be limited by the emission set resistance or current source.

Balanced slew rate follower

Material Science

• Two 2.2 K Ω resistors
• A 10 K Ω resistor
• One 0.01 μ F capacitance
• Three small signal PNP transistors (2N3906 or ssm2220 for Q2, Q3 and Q4)
• Three small signal NPN transistors (2N3904 or ssm2212 for Q1, Q5 and Q6)

explain

The circuit shown in FIG. 11 uses feedback to adjust the current in the emitter follower when the load current changes. The current of pulling the negative output can reach n (gain of NPN mirror) multiplied by the current of PNP Q3. In order to achieve the best transistor matching, Q3 and Q4 use ssm2220 PNP matching, and Q5 and Q6 use ssm2212 NPN matching (NPN current mirror gain is 1). Add a second ssm2212 in parallel with Q5 (to improve the gain of the current mirror).

Figure 11. Balanced yaw rate follower

hardware setup

The waveform generator is configured as a 1 kHz sine wave with a peak to peak amplitude of 4 V and an offset of 0. Oscilloscope input channel 2 is set to 1 V / Div.

Figure 12. Bread board circuit of balanced slew rate follower

Procedure steps

Configure the oscilloscope to capture multiple cycles of the measured two signals. The generated waveform is shown in Figure 13.

Figure 13. Waveform of balanced slew rate follower

Another way to improve the emitter follower is to reduce the effective re through negative feedback. The negative feedback factor can be increased by increasing the second transistor and the open-loop gain, so as to reduce the re. A single transistor is replaced by a feedback pair that provides 100% voltage feedback to the emission set of the first transistor. This feedback pair is often referred to as a complementary feedback pair. The value of R2 determines whether excellent linearity can be achieved because it determines the IC of transistor Q1 and the load of its collector.

Complementary feedback pair emitter follower

Material Science

• A 2.2 K Ω resistor
• A 10 K Ω resistor
• A small signal NPN Transistor (Q1 uses 2N3904)
• One small signal PNP transistor (2N3906 for Q2)

explain

The bread board connection is shown in figures 14 and 15.

Figure 14. Complementary feedback to emitter follower.

hardware setup

The waveform generator is configured as a 1 kHz sine wave with a peak to peak amplitude of 2 V and an offset of 0. Oscilloscope input channel 2 is set to 1 V / Div.

Procedure steps

Configure the oscilloscope to capture multiple cycles of the measured two signals. The generated waveform is shown in Figure 16.

Figure 16. Complementary feedback to emitter follower waveform

Question:

Can you give three characteristics of the starting emitter follower circuit?

You can find the answers on the student zone blog.

Figure 15. Complementary feedback to emitter follower bread board circuit

Introduction to the author

Doug Mercer graduated from Rensselaer Institute of Technology (RPI) with a bachelor’s degree in Electronic Engineering in 1977. Since joining ADI in 1977, he has directly or indirectly contributed more than 30 data converter products and has 13 patents. He was appointed ADI researcher in 1995. In 2009, he transformed from a full-time job and continued to serve as an ADI consultant as an honorary researcher, writing for the “active learning program”. In 2016, he was appointed resident engineer of RPI ECSE department. Contact: Doug [email protected]

Antonio miclaus is now a system application engineer of ADI company, engaged in ADI teaching projects, and works for circuits from the lab ®、 Develop embedded software for QA Automation and process management. He joined ADI in cluge napoka, Romania in February 2017. He is currently a master of science student in the master of software engineering program of beibisboyer University and holds a Bachelor of Science Degree in electronic and telecommunications engineering from kluz napoka University of science and technology.