Flight control computer is the core device of modern missile guidance and control system. Its performance is directly related to the precision of precision guidance and the probability of killing target. In recent years, the missile borne equipment such as steering gear, seeker and inertial navigation system is developing towards the digital direction. Therefore, it is very important to design a general flight control computer platform which can be compatible with multiple digital devices. The traditional single processor core flight control computer is difficult to guarantee the data processing speed at the same time of multi-channel asynchronous data receiving and sending, which is difficult to meet the requirements of modern missiles. This paper presents a general digital flight control computer platform based on DSP + FPGA structure and 422 external interface. This platform can give full play to the operation speed of DSP and realize flight control algorithm. The dual RAM buffer mechanism based on FPGA can solve the problem of asynchronous serial data real-time synchronous data processing and meet the requirements of flight control system.
Design idea and working principle
1.1 design idea
For the flight control computer with single DSP core, if it wants to send and receive multi-channel asynchronous serial data, it will occupy multiple interrupts, resulting in the delay of interrupt response and data loss. At the same time, multi-channel interrupt will also affect the real-time performance of data transmission. The flight control computer has high requirements for data integrity and real-time performance. The traditional single DSP core can not meet the requirements of multi digital equipment on missile. Because of the powerful parallel processing ability of FPGA, the method of adding a FPGA to receive and receive asynchronous serial data is adopted to make up for the defect of single DSP core. The structure of DSP + FPGA can liberate DSP from the tedious external interface management, give full play to the advantages of DSP, improve the operation efficiency, and easy to maintain and expand.
1.2 working principle of flight control computer
The general working process of the flight control computer is as follows: after the flight control computer is powered on, it conducts self-test and sends the “missile existence” command to the carrier aircraft. The flight control computer receives the binding information of the carrier, completes the initial alignment, and sends the “allow launch” command to the carrier. When the seeker detects the target and sends guidance data to the flight control computer, the flight control computer sends the “target interception” command to the carrier. After judgment and decision-making, the carrier gives the “launch” command to the flight control computer. After the launch, the flight control computer timing the flight time, and according to the existing control rate, combined with the ins and seeker input, the flight control calculation is carried out, and the four rudder control signal signals are obtained to control the missile movement; and the received INS data, seeker data, rudder control value and other contents constitute telemetry information, and send it to the observer.
2. Structure and hardware design
According to the working principle of flight control computer, it has the following functions:
It can send and receive binding, INS, seeker and telemetry data;
It can realize the guidance rate and complete the navigation data calculation function;
It can control the actuator steering gear.
RS422 communication protocol has the characteristics of strong anti-interference ability, long transmission distance and simple implementation, which has been widely used by various digital devices. 422 communication protocol is adopted for the external communication interface of the missile borne aircraft. According to the function of flight control computer, the system should at least include five channels of data communication, including binding, inertial navigation, seeker, telemetry data receiving and transmitting, and steering gear control. The input and output of the switch value is also needed for the missile borne aircraft to receive and receive the switch values such as “missile presence”, “target interception” and “allowable launch”. Therefore, the external interface of FPGA includes 5-channel RS422 and 8-bit DIO communication interface. The system structure diagram is shown in Figure 1 (the description of xinf interface and dual port RAM in the figure is shown in part 4 of this paper).
DSP adopts high-performance floating-point processor of TI company with 150 MHz main frequency. Compared with 2812, the performance is greatly improved, which is widely used in control system. The cyclone II series of Altera is selected for FPGA, which fully meets the application requirements. The minimum system composed of DSP and FPGA is mainly composed of power supply, reset circuit, crystal oscillator, burn write interface and so on. The power supply chip tps7 67d301pwp can provide 3.3 V working voltage and 1.9 V core voltage for DSP; the core voltage of FPGA is obtained by asm1117-1.2 voltage stabilization. MAX809S is used for DSP reset chip, 30 MHz active crystal oscillator is used for crystal oscillator, and 50 MHz active crystal oscillator is used for FPGA. Epcs1 is selected as the configuration chip with a capacity of 1m bits and is written in as mode.
The external RS422 interface is implemented by max3491 protocol chip. Max3491 converts the TTL level of FPGA into 422 differential level, and communicates with the equipment on the missile. Due to the weak driving ability of FPGA pins, 74ln244 chip is used for external 8-bit DIO to enhance the driving ability.
3 software design
DSP communicates with FPGA through xinf interface. DSP transmits the address to FPGA, and FPGA decodes the address to corresponding external device data.
3.1 FPGA Software Design
The main function of FPGA is to send and receive the input and output of the switch value at the same time of 5-channel RS422 serial port data, and exchange data with DSP. FPGA can use process statements to realize parallel operation, and the operation of all peripherals is real-time parallel and has no influence on each other.
3.1.1 serial communication
Firstly, the clock is divided into 8 times the baud rate of the serial clock. When receiving data, according to the characteristics of serial communication, the low-level start bit is first determined. After the start bit is detected, a byte 8-bit level is collected in strict accordance with the relationship of one bit every eight clocks. In this case, voting mechanism is adopted, that is, sampling 3 times during 8 clocks, and 2 times of the same level shall prevail. Experiments show that the voting mechanism can greatly eliminate the random noise interference and reduce the bit error rate of serial communication. After receiving the data, it is stored in the corresponding dual port RAM, waiting for DSP to read it. The process of receiving serial data is shown in Figure 2.
During data transmission, the data to be sent is read out from the dual port RAM. According to the serial port clock, the start bit (low level) is sent first, and then the 8-bit data is converted into serial “0” / “1” by shift register. It is mainly realized by the following statements:
txd_buf（6 downto 0）《=txd_buf（7 downto 1）;
Where TXD is the 1-bit logic level to be transmitted, TXD_ BUF stores the data to be sent. The sending process is shown in Figure 3.
The program designed according to the above process is tested in FPGA. The serial port of FPGA is connected with PC, and it works continuously for 3 minutes at 115200 baud rate, and there is no error byte in sending and receiving.
3.1.2 dual RAM buffer mechanism
Since the baud rate of serial peripheral is 115200, which belongs to low speed peripheral, dual port RAM is used as buffer between serial port data and DSP. Since the FPGA is equipped with on-chip RAM, it is possible to use the IP core of the development environment to generate on-chip dual port ram without additional on-chip RAM devices (Fig. 1). Entity definition and read / write timing of dual port RAM:
The last byte in each ram is taken as the status word reflecting the RAM storage status. The meaning of ram status word is as follows:
Bit0:1 – new data frame received by serial port 0 – no new data frame;
Bit1: 1 – the data has been read, 0 – the data has not been read;
Ins and seeker transmit a frame of data to missile borne aircraft every 6 ms, and store the data in dual port RAM. At the same time, bit0 is set to “1” and Bit1 is cleared, that is, RAM status is “new data frame not read”. Since the data of ins and seeker are not synchronized, DSP queries the ram status word every 1ms. If a new data frame is received (bit0 = 1), the RAM data is read and the “data is read” position 1 (Bit1 = 1). In this way, the delay of data sent by ins and seeker to DSP is less than 1 ms, so the data of ins and seeker are real-time synchronous.
If the serial port and DSP operate ram at the same time during receiving data through serial port, it may cause DSP to read frame disordered data. In order to ensure the integrity of the data frame and not to read ram at the same time, the dual RAM buffer mechanism is adopted, that is, each serial port is configured with two dual port RAM as buffer, as shown in Figure 5. The serial port data receiving program queries the status words of Rama and RAMB. If Bit1 = 1, the received data frame is stored in the corresponding ram. After completion, bit0 is set to 1 and Bit1 is cleared to 0. This cycle is 6 ms. At the same time, DSP queries Rama and RAMB every 1 ms. if bit0 is 1, it reads the data frame in the corresponding ram and clears bit0 to 0. Bit1 is set to 1. The sending process of serial port data is similar to receiving, and the direction of data transmission is opposite.
Using double RAM buffer mechanism, the serial port and DSP do not access the same RAM area at the same time, which avoids frame error and frame loss, and ensures the real-time data transmission.
3.2 DSP software design
DSP software design adopts modular design method, which is divided into application layer and bottom layer software. The application layer software mainly realizes the flight control flow and flight control algorithm; the bottom software mainly realizes the conversion of data format, so as to exchange data between DSP bus and FPGA.
3.2.1 application layer software design
The external ins and seeker generate data once every 6 ms, and the DSP starts the timer interrupt of 1ms. In the interrupt, the status word of dual port RAM is queried every 1 ms to judge whether there is new data generated. In this way, the delay of data acquisition will not exceed 1 ms. The period of flight control calculation is 6 ms and the period of telemetry data transmission is 12 Ms. the flight control calculation and telemetry data transmission are completed in timer interrupt program.
The interrupt service program runs once every 1 ms. each time, it first queries whether the seeker and INS have updated data, and then reads the new data and stores it in the global structure. Every 6 ms, the new data obtained from the global structure is used to calculate the flight control command, and the output angle of the steering gear is obtained, and the rudder control command is output to control the steering gear. The flow is shown in Figure 6.
3.2.2 bottom software design
DSP bottom software mainly completes the external data exchange and data format conversion. DSP generates read-write timing (as shown in Fig. 2 and Fig. 3) through xinf, and FPGA designs corresponding timing to complete data exchange between them.
DSP application layer software uses floating-point numbers, but only binary numbers can be transferred between DSP and FPGA, so it is necessary to convert floating-point numbers and binary numbers according to IEEE standard. According to the IEEE standard, 32 bits, or 8 bytes, can be used to represent a floating-point number. If four bytes representing floating-point numbers are combined into a 32-bit integer integer inte32, the floating-point number can be obtained by cast. The conversion function is as follows:
You can convert floating-point numbers to integers in a similar way. The underlying software implements data conversion according to the above method, and provides layer call.
4 system verification
The hardware in the loop simulation platform is composed of upper computer, inertial navigation, steering gear and three-axis turntable. As shown in the figure, the upper computer is used to simulate the missile dynamic model and seeker information, and control the motion of three-axis turntable to simulate the missile attitude. The motion information of the missile is measured by ins and sent to the flight control computer. The flight control computer calculates the control value of the steering gear according to the motion information, controls the steering gear rotation, and sends the telemetry data to the upper computer. The upper computer collects the actual feedback angle of the steering gear, replaces it into the missile dynamic model, calculates the missile attitude, and controls the three-axis turntable, thus forming a complete hardware in the loop simulation.
In the simulation experiment, the control algorithm is directly realized by the mathematical model of the control system in the simulation computer without access to the flight control computer, and the trajectory of the missile obtained is shown in Fig. 8; the flight control computer is connected to the simulation loop, and the flight control computer realizes the guidance and control algorithm, and the motion trajectory obtained is shown in Fig. 9.
From the comparison between Fig. 8 and Fig. 9, it can be seen that the flight control system works normally after the flight control computer is connected, the flight trajectory of the missile is basically consistent, and the control effect of the flight control computer is ideal.
This paper presents a design method of flight control computer based on DSP + FPGA. Its performance is verified in the hardware in the loop simulation system and meets the design requirements. The problem of real-time synchronization of data frame in the presence of multi digital missile borne equipment is solved. Because FPGA can realize all kinds of timing sequence by programming, the flight control computer can be extended to other digital device interfaces except RS422 external interface, which can meet the practical application requirements of modularization and generalization.