Achronix The latest 7Nm based on TSMC The speedster7t FPGA device of FinFET technology contains a revolutionary new two-dimensional network on chip (2d-noc) NoC）。 2D NOC, like highway network running on FPGA programmable logic structure, provides ultra-high bandwidth (~ 27tbps) for data transmission of FPGA external high-speed interface and internal programmable logic.
NOC uses a series of high-speed row and column network paths to distribute data in the whole FPGA, so as to distribute data traffic in the whole FPGA structure in a horizontal and vertical way. Each row or column in the NOC has two 256 bit, one-way, industry standard Axi channels that can run at 512gbps (256bit x 2GHz) in each direction.
NOC provides several important advantages for FPGA design, including improving design performance. Reduce the idle logic resources, and reduce the risk of layout and routing congestion in high resource occupancy design. Reduce power consumption. To simplify the logic design, NOC replaces the traditional logic to do high-speed interface and bus management. Realize the real modular design.
This paper uses a specific FPGA design example to show the important role of NOC in FPGA internal logic interconnection. This design is mainly to achieve triple data encryption and decryption algorithm (3DES). This algorithm is a mode of DES encryption algorithm. It applies DES encryption algorithm three times for each data block, and increases the security by increasing the key length of Des.
In the FPGA design, we put the I / O pins on the top, bottom, left and right of the FPGA. The data coming in from the upper pin is decrypted by logic 1, and then sent to logic 2 through blue routing. After encryption, it is sent out from the lower pin. The data coming in from the left pin is decrypted by logic 3, and then sent to logic 4 through red routing. After encryption, it is sent out from the right pin.
The problems encountered in this design are as follows: the connection delay between the encryption and decryption modules is too long, and the design performance will be greatly limited if the pipeline register is not added. However, because the bit width of the connection bus is 256 bits, adding several levels of pipelined registers will take up a lot of extra register resources.
The connection bus between the upper and lower modules and the connection bus between the left and right modules are crossed. If the design is a little more complex, it may encounter local congestion in layout and wiring, which will greatly increase the time of tool layout and wiring. The above two problems are also more or less encountered by the majority of FPGA designers in complex FPGA design. The reasons may be due to the complexity of the design, the limitation of the hardware platform, or the design must connect peripheral hard IP in different locations.
The emergence of NOC has solved the problems we encountered above. NOC provides bidirectional 288 bit raw data mode for FPGA logic interconnection. Users can use the 288 bit signal for direct logic connection or custom protocol interconnection. There are two network access points (NAPs) at each intersection of NOC. Users can connect their logic to NOC by instantiating the primitive or macro definition of nap.
In this way, by instantiating nap on the 3DES encryption and decryption modules, the NOC interconnection between the 3DES encryption and decryption modules can be realized. In this way, the user design is simplified, and the design performance is greatly improved, from 260MHz to 750MHz. As can be seen in Figure 6, a large number of connection buses between logics can no longer be seen, and the bus connections are all taken over by NOC. In the back-end layout and wiring diagram, only the green clock routing and the logic routing inside the white module can be seen.
This paper mainly wants to show FPGA designers how to use NOC to interconnect the internal logic of FPGA through such an example, so as to provide FPGA designers with another way of thinking. In the traditional FPGA design, when the performance cannot be improved and the layout and wiring are congested, can we consider using the new generation speedster7t FPGA of acronix to simplify and accelerate the user’s design.