1 Overview

Ad1555 is an oversampling Σ- Δ The regulator contains a programmable gain amplifier (PGA), which can be used in the measurement field of low frequency and large dynamic range. The device technically adopts analog input linear output mode. It can form a high-performance analog-to-digital converter in combination with ad1556 digital filter / sampler. Since continuous time analog modulators are used, they do not require external de stepped filters. In addition, the design method of simplifying the system before and after using programmable gain also expands the dynamic range and reduces the area of the circuit board. At the same time, the adoption of low power consumption and standby simulation makes ad1555 an ideal application choice in battery powered data acquisition system.

Ad1555 is a BiCMOS device. It is a high-performance analog device composed of bipolar CMOS transistors. The ad1555 and ad1556 are packaged in 28 pin and 44 pin packages, respectively.

2-pin function

The pin arrangement of ad1555 and ad1556 is shown in Figure 1.

24 bit Σ- Δ Functional characteristics and application analysis of analog-to-digital converter ad1555 / 6

2.1 pin definition of ad1555

The pins of ad1555 are defined as follows:

Agnd1 (1 pin): Analog ground;

Pgaout (2 pins): programmable gain amplifier output;

+VA: (3, 26 pins): analog power supply voltage positive terminal, rated value is + 5V;

-VA: (4, 20, 21 pins): negative terminal of analog power supply voltage, with rated value of – 5V;

Ain (+) (pin 5): multi-channel composite input, used to input the non inverter signal of PGA multi-channel composite input;

Ain (-) (pin 6): multi-channel composite input, used to input the inverter signal of PGA multi-channel composite input;

Tin (+) (pin 7): multi-channel composite input, used to input the inverse detection signal of PGA multi-channel composite input;

Tin (-) (pin 8): multi-channel composite input, used to input the non inverter detection signal of PGA multi-channel composite input;

NC (9 pins): Factory defined pins. The pin is suspended under normal use;

CB0 ~ CB4 (10 ~ 14 pins): regulator control end. These pins can be used to control multiplex selection of ad1555, gain setting of PGA and standby mode. When ad1555 and ad1556 are used together, these pins are generally directly connected with CB0 ~ CB4 output pins of ad1556. CB0 ~ CB2 are mainly used to set PGA gain or enter standby mode. CB3 and CB4 are mainly used to select the multi-channel composite input voltage of PGA;

Mflg (15 pin): error bit of modulator, high level in case of out of range signal;

DGND (16 pins): digital ground;

MDATA (17 pin): the output port of the modulator, and the output bit stream signal is effective in about 0.5 MCLK cycles;

MCLK (pin 18): clock input signal, about 256Hz. When ad1555 is in power down state, MCLK remains unchanged.

Agnd3 (22 pin): Analog ground, as the reference ground of refin pin;

Refcap1 (23 pin): DAC reference filter, which provides reference input for the modulator, and connects a 22 between refcap1 and agnd3 μ F external tantalum capacitor can filter out external reference noise;

Refcap2 (24 pins): reference filter;

Refin (25 pin): reference input;

Agnd2 (27 pins): Analog ground;

Modin (28 pin): modulator input, usually directly connected to pgaout.

2.2 pin function of ad1556

NC (1, 21, 27, 28, 33, 37 feet): suspended;

Pag0 ~ pga4 (pins 2 ~ 6): PGA and multi-channel composite control input can be used to set the logic potential of cb0-cb4 and the corresponding status bit in the structure register during restart or hardware mode;

Bw0 ~ BW2 (pins 7 ~ 9): output rate control terminal, which can be used to set the sampling rate of digital filter and relevant status bits in structure register when restarting or hardware mode;

H / S (10 pin): Hardware / software mode selection port. At high level, it is the hardware working mode. At low level, the device is set to write timing or continuous write timing to the structure register;

VL (11, 22, 44 pins): digital power supply, rated 3.36v or 5V;

DGND (12, 23, 24, 34 pins): digital ground;

SCLK (13 pin): serial data clock input, which can be used to synchronously transmit the write signal operation of DIN pin and the read signal operation of dout pin;

Dout (pin 14): serial data output, which starts at the beginning of the read operation. The data changes at the rising edge of SCLK and is valid before the falling edge of slck;

Drdy (pin 15): the data is ready, the output is at high level, and the data is ready to enter the output data register; The output is low level, indicating that the read operation is completed;

CS (16 pin): chip selection end, low level, pins DIN, dout, and SCLK are activated; For level, these pins are invalid;

R / w (pin 17): read / write selection, set to high level and CS to low level, activate read operation; When it is set to low level, it can be written by DIN pin;

Rsel (pin 18): register selection, set to high level, and the conversion structure of digital register is output by dout pin; When it is set to low level, the contents of the status register are output by the dout pin;

DIN (pin 19): serial data input. During read operation, it can be loaded from the input conversion register to the structure register. It starts from the highest bit and is valid at the falling edge of SCLK;

Error (pin 20): error flag. The output is low level, indicating that there is an error in the modulator or digital filter. At this time, the error position of the status register is 1;

Reset (pin 25): restart the filter, input the high level, clear the relevant error bits of the status register, and set the status bits of the relevant hardware pins in the structure register (this operation should be carried out under the power supply state);

Pwrdn (pin 26): power down hardware control. When pwrdn is at high level and slkin is at the first falling edge, it is in power down mode;

Scel (29 pin): filter input selection, this pin

For high level, Tdata pin is used as the data input of digital filter; The pin is at low level, and the modata pin is used as the input;

Tdata (30 pin): test data input terminal, input test data to filter;

Sync (pin 31): synchronization input. It clears the ad1556 digital filter through this pin to synchronize with the filter convolution;

CLKIN (32 pin): clock input, rated frequency 1.024mhz;

MCLK (35 pin): modulator clock, used to provide modulator sampling frequency, sampling at 1 / 4 of CLKIN frequency;

MDATA (36 pin): modulator data. The input pin receives the ones-density bit stream from ad1555 and inputs it to the digital filter;

Mflg (38 pin): modulator error, used to check the existence of out of bounds error in the modulator;

CB0 ~ CB2 (pins 43 ~ 39): modulator control terminal, which is mainly used to set PGA gain or guide into PGA standby mode. CB3 and CB4 are used to select the multi-channel composite voltage required by PGA.

3 circuit description

3.1 adjustment circuit of ad1555

The ad1555 contains an analog multiplexer, a fully differential programmable gain amplifier and a four-stage Σ- Δ Modulator. The analog multiplexer allows full differential input, internal reference ground or external full bias reference voltage to be selected from four external inputs. The fully differential programmable gain amplifier has five gain settings, namely 1, 2.5, 8.5, 34 and 128. Five different input ranges are 16V, 636mv, 187mv, 47mv and 12.4mv (determined according to the input of pins cb0-cb4). The rated sampling frequency of the modulator is 256khz. The output bit stream of ad1555 is proportional to the input voltage. The bit stream can be filtered by finite pulse low-pass digital filter. Finally, 24 bit word data is output through ad1556 serial interface. The cut-off frequency and output rate of the filter can be programmed by on-chip registers or controlled by hardware through data input pins.

The dynamic performance and equivalent input noise of ad1555 are different due to different gain and output rate. Selecting different gain settings of PGA can expand the total dynamic range of the system to 146db.

The ad1555 operates at dual analog inputs (± 5V), while the digital part operates at + 5V. Ad1556 operates under 3.3V or 5V power supply. Each device can be used in low power consumption and standby state.

3.2 ad1556 digital filter

Ad1556 is a linear low-pass FIR digital filter, which takes the output bit stream of ad1555 for filtering and sampling. Since the ad1556 uses a user selectable 7-Stage filter, it has 7 different sampling rates, ranging from 1 / 16 to 1 / 1024. The rated input word rate of ad1556 is 256kbit / s, and the output word rate ranges from 16KHz to 250kHz. The maximum bandwidth flatness of ad1556 filter is ± 0.05db, and the maximum output bandwidth attenuation is – 135db (except that owr = 16KHz, its bandwidth attenuation is – 86db). Its bandwidth frequency and – 3dB frequency are 37.5% and 41% of the output word rate respectively. The noise generated by ad1556, even the noise generated by word truncation, may have a small impact on the dynamic range of ad1555 / ad1556 chip. In addition to being used with ad1555, ad1556 can also be used with other Σ- Δ Modulator combination.

In structure, the main structure of ad1556 filter is a two-stage filter. The sampling rate of the second stage is 4 (when the output word rate is 250Hz, the sampling rate is 8), and each filter is a linear corresponding equal wave fir device. The summation is performed by a linear symmetric data sampler, and then the convolution operation is performed by a multiplier and an adder. Its structure is shown in Figure 2. The structure of the two pole filter is similar to that of the first stage, and the main difference is the use of a real multiplier. The multiplier, adder and output buffer are 32, 35 and 24 bit word width respectively. Truncating word bits will not affect the dynamic performance of ad1555 / ad1556 chip.

4 connecting circuit of ad1555 and ad1556

The typical application circuit connection diagram composed of ad1555 / ad1556 components is shown in Figure 3.

5 Conclusion

Ad1555 is oversampled Σ containing PGA- Δ Modulator, combined with ad1556, can form a high-performance analog-to-digital converter, which can be applied to seismic data detection system, automatic test and other devices.

Responsible editor: GT

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