Circuit functions and advantages

The circuit shown in Figure 1 is a dual channel, low latency and low power PHY card, which supports 10 Mbps, 100 Mbps and 1000 Mbps speeds, and is suitable for industrial Ethernet Applications with linear and ring network topologies.

Dual channel supports linear and ring network topologies commonly used in industrial detection, control and distributed control systems. Adin1300 Ethernet PHY is widely tested for the robustness of electromagnetic compatibility (EMC) and electrostatic discharge (ESD), supports automatic negotiation, and can link with remote PHY devices at the highest general speed advertised. IEEE 1588 timestamps in PHY reduce the timing uncertainty in real-time applications, and enhance the detection of redundancy and link loss in real-time applications.

The circuit consists of two independent 10 Mbps, 100 Mbps and 1000 Mbps Phys. Each PHY has a high efficiency Ethernet (EEE) PHY core and all related general analog circuits, input and output clock buffer, management interface, subsystem register, media access control (MAC) interface and control logic.

The design is powered by the host field programmable gate array (FPGA) mezzanine card (FMC) development board without external power supply. Software programmable clock supports media independent interface (MII), reduced MII (RMII) and reduced Gigabit MII (rgmii) MAC interface modes. RJ45 ports with integrated magnetic components make the solution as compact as possible.

The solution supports up to 150 meters of cable at Gigabit speeds and up to 180 meters at 100 Mbps or 10 Mbps speeds. This solution is usually used for ring or bus topologies. Adin1300’s auto negotiation feature allows connection with other PHY devices at the highest speed supported.

poYBAGDlalWAcukBAADvfg3IAHQ444.png

Figure 1. Simplified block diagram of eval-cn0506-fmcz (decoupling and all connections not shown)

Circuit description

Ethernet

Ethernet is the most common packet based physical connection type for data network applications in local area network (LAN). It is defined by several sections and specifications of IEEE 802.3 standard.

Ethernet has different speeds and transmission media. However, this circuit note focuses on 10Base-T, 100base-tx and 1000BASE-T on straight through or cross, CAT5e or CAT6 twisted pair cables.

Linear and ring network topologies

Typical industrial Ethernet network is deployed in linear or ring topology. Compared with star networks, linear and ring network topologies have shorter routing length, and ring networks have a redundant path (see Figure 2). Each device connected to a linear or ring network requires two Ethernet ports to pass Ethernet frames along the network.

poYBAGDlanmAXIMbAADwB2jAU3I304.png

Figure 2. Linear and circular topologies

PHY

PHY is a physical interface transceiver that implements the physical layer function of the open system interconnection (OSI) model. PHY encodes and decodes the data sent and received between devices to maintain the integrity of frames and packets (see Figure 3).

PHY hardware configuration binding resistor

The adin1300 can be configured as power on ready to establish a link. This PHY hardware configuration uses external binding resistors to provide a known configuration for power up operations in unmanaged applications. In unmanaged applications, users usually do not configure PHY on MDIO. Instead, the unmanaged application relies on the PHY hardware configuration to start adin1300 with the appropriate configuration so that it is ready to link with the remote PHY partner. When adin1300 is powered on, the hardware binding pin samples when the device is out of reset state, so that PHY device knows how to configure various functions.

The hardware configuration mode of this circuit is speed, PHY address, auto mdix and MAC interface. Eval-cn0506-fmcz contains resistors of various sizes to support various combinations and has a specific default configuration. If you need to change the default hardware configuration, you can insert or remove resistor elements.

For more information about using other features and functions, such as energy efficient Ethernet (EEE), energy detection shutdown, shutdown speed, and software shutdown, refer to the adin1300 data book.

poYBAGDlasCAdH4EAACLTiq15W0616.png

Figure 3. Typical network sensor with PHY device

Physical layer MAC interface

MAC interface is a wired medium on cn-0506. There are three MAC interface options: rgmii, RMII or MII. Rgmii supports all speeds up to 1000 Mbps, while MII and RMII support 10 Mbps and 100 Mbps respectively. Rgmii is the default interface of cn0506.

There are two ways to choose which MAC interface to use: binding external resistance by hardware, or using software register configuration. MACIF_ Sel0 and macif_ Sel1 is a multifunctional pin in adin1300 (see adin1300 data manual for more information). For cn-0506, macif can be configured according to table 1_ Sel0 and macif_ Sel1 pin to select MAC interface. Please note that macif_ Sel0 and macif_ There is a weak pull-down resistance inside the sel1 pin. Therefore, if there is no external binding resistor, the default MAC interface is rgmii with 2 ns delay.

Table 1. MAC interface selection

In this circuit note, MAC interface selection is completed by software configuration, that is, Ge in adin1300 is used_ RGMII_ CFG and GE_ RMII_ CFG register. If users prefer to configure MAC interface in hardware, space is reserved for external pull-up and pull-down resistors. However, since no resistor is installed, PHY on eval-cn0506-fmcz is powered on using the default rgmii interface.

PHY address

There are four PHY address pins (phyad)_ x) , allowing users to configure PHY to any of the 16 PHY addresses. PHY addressing enables the system to obtain up to 16 independent controllable channels from a single controller.

Eval-cn0506-fmcz is currently hardwired to a specific address, but can be changed by changing the configuration resistance of each channel. The current assigned address of channel 1 is 0001, and the current assigned address of channel 2 is 0010.

Programmable MAC interface clock

Adin1300 has three MAC interface options: MII, RMII or rgmii. For rgmii and MII interfaces, adin1300 needs a 25 MHz clock, while RMII needs an external 50 MHz clock. In the user application, the user can choose to put the 25 MHz crystal oscillator in XTAL_ I and XTAL_ If RMII is used, the host controller, MAC interface or switch chip can directly provide the 50 MHz clock to PHY.

Eval-cn0506-fmcz includes two I2C programmable clocks (Y1 and Y2) from 100 kHz to 125 MHz to support the corresponding clock requirements of different MAC interfaces of adin1300.

By default, the clock for each channel is set to 25 MHz when powered on. When using RMII MAC interface, the clock can be programmed to 50 MHz.

The two clocks have the same I2C address, but by using the I2C address converter ltc4316, these clocks can be programmed to different addresses. Ltc4316 performs XOR operation on the incoming address and converts each incoming bit into a user configurable conversion byte set by the resistance divider network of the chip.

MDI interface integrated magnetic components

Generally, MDI interface connects adin1300 to Ethernet through transformer and RJ45 connector. Cn-0506 uses RJ45 connector with integrated magnetic components. The integrated magnetic components in RJ45 connector can usually improve the electromagnetic interference (EMI) shielding, and the size is smaller. Compared with the use of discrete magnetic components, the required wiring is shorter.

The integrated magnetic components include RJ45 connector, common mode choke, isolation transformer, led, decoupling capacitor and termination resistor. Due to different overvoltage requirements in the design, or if different layouts are required for specific EMI, the design can choose to use discrete magnetic components.

Power Supply

In order to reduce the number of power supply, the analog circuit power supply of adin1300, MDIO and MAC interface is obtained from the 3.3 V power supply rail of FPGA through ferrite beads to reduce the noise entering the system.

Adin1300 digital core needs 0.9 V power supply. The power supply is obtained from 3.3 V supply rail by lt3502 pulse width modulation (PWM) buck DC-DC converter; The converter converts FPGA 3.3 V power supply to 0.9 V, and consumes 0.45 w carrier power.

Software overview

The FPGA reference design provided for cn-0506 is independently configured with each adin1300. Each PHY (adin1300) is connected to the specified MAC interface. Three interface modes are supported between adin1300 and FPGA: rgmii, MII and RMII.

Each mode has a separate hardware design language (HDL), because some modes require a converter, such as Gigabit MII (gmii) to rgmii. The working mode must be selected in HDL to be consistent with the mode users want to use in Linux.

Eval-cn0506-fmcz is connected to the standard low pin count (LPC) FMC connector, and the software design can be transplanted to many different FPGA development boards.

Linux device trees supported by different modes and carrier combinations can be found on cn0506 HDL page. For more information about ADI’s standard Linux image, see the FPGA image user’s Guide.

Circuit board layout considerations

Ethernet signal layout is very important, especially at Gigabit speed. The signal is routed to the RJ45 Jack in the form of a 100 Ω controlled impedance pair.

When operating at a lower clock rate, the data and clock signals to the carrier have edge rates, which requires careful layout. The signal on eval-cn0506-fmcz should be kept as short as possible. When connecting cn-0506, the signal wiring length and impedance matching on the carrier board must be carefully considered. These factors are very important to the overall speed and performance of cn-0506, but they must be considered separately.

Figure 4 shows the largest drop of 1000BASE-T from V2 to V1 – 98.7%.

pYYBAGDlav-AW0lXAAFAt97L7AE424.png

Figure 4. Peak PHY differential output voltage

Performance results

Cn-0506 is used for some tests, including pattern verification test, speed test and cable length drive test.

Eval-cn0506-fmcz was tested in different modes, and the cable length increased gradually. The results of 4 m cable and 154 m cable are listed in detail in Table 2 and table 3 respectively, and there is no packet loss.

Table 2 and table 3 show the frame checker count register (FC) of adin1300 at local and remote Ethernet PHY positions for short cable transmission and long cable transmission, respectively_ FRM_ CNT_ H and FC_ FRM_ CNT_ 50) And receive error count register (Rx)_ ERR_ Read back value of CNT).

Common changes

If the application does not require speeds up to 1000 Mbps, adin1200, a single port Ethernet transceiver with lower power consumption, can be used, with a maximum speed of 100 Mbps.

As an alternative to I2C bus converter, ltc4317 is a single input, dual output I2C address converter, while ltc4318 is a dual input and output I2C bus converter.

If the application does not need RMII support, only using a fixed frequency 25 MHz crystal oscillator can simplify the clock scheme.

Circuit evaluation and test

Data integrity and bandwidth are very important in industrial networks. Data loopback test can verify the whole system, including eval-cn0506-fmcz, cable and connector. For complete details on setup and testing, see cn0506 user’s Guide.

Equipment requirements

The following equipment is required:

Eval-cn0506-fmcz circuit evaluation board

· CAT6 Ethernet cable

· zc706 FPGA development board

· SD card

Wireless keyboard and mouse with USB a dongle

· Mini USB OTG adapter

High definition multimedia interface (HDMI) male to male cable

· HDMI monitor

ADI’s Linux image, configured to be used with cn0506

Start using

Prepare the SD card as detailed in the ad-fmc-sdcard Quick Start Guide for zynq and Altera SOC, including the following:

1. Download the latest FPGA Linux image.

2. Format the SD card.

3. Burn FPGA Linux image to SD card.

4. Copy the boot.bin and device tree file of cn-0506 to the boot partition of SD card.

Function block diagram

Figure 5 shows the functional block diagram of the test setup.

poYBAGDla4aAMqmGAACx53qfsko528.png

Figure 5. Functional block diagram of test setup

set up

Perform the following steps to set up the test:

1. Use LPC FMC connector to install eval-cn0506-fmcz on zc706 FPGA development board, and fix it with a 10 mm support.

2. Insert the pre configured SD card into Xilinx zc706.

3. Connect Ethernet cable between two RJ45 Ethernet jacks to establish loopback.

4. Connect HDMI cable between HDMI monitor and Xilinx zc706.

5. Plug the Mini USB OTG adapter into the Mini USB port of Xilinx zc706.

6. Connect the wireless keyboard and mouse to the USB OTG adapter with USB A-type dongle.

7. Connect the power connector to Xilinx zc706 and plug the other end into the wall adapter.

test

Test the system in loopback mode, that is, generate a large amount of data, send the data from one channel to another, and then send it back.

Figure 6 shows the physical photo of eval-cn0506-fmcz circuit evaluation board.

pYYBAGDla5OAPD9UAAKmjKGhv94091.png

Figure 6. Eval-cn0506-fmcz circuit evaluation board

Leave a Reply

Your email address will not be published. Required fields are marked *