The analog-to-digital conversion discussed in this design example will produce a bit stream, and its average value will change with the change of analog input average value. Delta sigma( Δ-Σ) The SPICE simulation diagram of the conversion demonstrates its working principle. This analog-to-digital conversion will produce a bit stream, and its average value will change with the change of the average value of the analog input. Please see Figure 1.

Δ-Σ The working principle of the converter and the demonstration and analysis of SPICE simulation diagram

Figure 1: delta sigma conversion.

The D-type flip-flop is controlled by the clock at a specific frequency. The Q output of the flip-flop is sent back to the inverting input of the comparator after low-pass filtering, and the non inverting input comes from the signal input. If the signal input is higher than the output of LPF 1, the D input of the trigger is high level, and the Q output will become high level when the next clock pulse arrives. This will raise the voltage at the output of LPF 1 above the input level. At this time, the comparator will change the D input to low level and the Q output to low level.

In the repeated transformation of Q output state from high to low, the average output of LPF 1 tends to be equal to the signal input. Although there has never been real equality, there is indeed this trend.

At the same time, the fluctuation of Q output forms a digital bit stream, which can be easily transmitted over a considerable distance, while another filter LPF 2, which is the same as LPF 1, can obtain the bit stream and reconstruct the original signal input.

The following SPICE simulation ignores all the specific details of level conversion and demonstrates its working principle.

Figure 2: delta sigma conversion simulation.

Since the logic level of D-type trigger U1 remains the same, V2 needs to be used to make everything compatible. The above three traces in Figure 2 are the signal output generated after reconstructing the 1kHz input using 1MHz, 100kHz and 64khz clock frequencies respectively. The logic waveform shown in the figure is only 64khz.

Responsible editor: GT

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