The resolution and speed of the data converter have been continuously improved. I still remember that about 25 years ago, at a meeting attended by Tektronix, I collectively discussed the future development direction of data converter. I can’t even imagine that the resolution can be improved from 16 bits to 24 bits. But, ΔΣ The architecture of the converter can achieve such an exciting resolution breakthrough.

ΔΣ The converter can achieve 24 bit conversion results. Although this sounds exciting, in order to achieve the best results, we still need to choose many parameters correctly. With the adjustment of sampling, modulation clock and PGA, the performance of the same data rate will be different. When optimizing data conversion results, it is not easy to fully understand these aspects. Other problems include input impedance, filter response, anti aliasing, and long-term drift.

ΔΣ Converter introduction

ΔΣ The advantage of the converter is that it transfers most of the conversion process to the digital domain. This enables it to integrate high-performance analog and digital processing. The analog element adopts a single comparator, integrator and 1-bit DAC. Since the 1-bit DAC has only two outputs, it is linearized over the entire voltage range. This high level of linearization is ΔΣ One of the reasons for the high accuracy of the converter. The final absolute accuracy mainly depends on the accuracy of the reference voltage.

ΔΣ Modulator

ΔΣ Application advantages and high precision performance of the converter

Figure 1 ΔΣ Modulator

Let’s look at a simple example ΔΣ The waveform in the modulator (see Figure 1). The proportion of input signal X1 is 1 / 4. The input signal minus the DAC output signal (x5) is a pulse train, one cycle is low level and three cycles are high level (x2). The latch comparator output (x4) is a continuous bit stream fed back to the digital filter, and its 1:0 ratio is directly related to the ratio of the input voltage to the full range input range.

Each vertical line indicates that the latch comparator output is controlled by the modulation clock. In order to analyze its operation, it is best to start with the output, regard it as the driving signal, and then close the loop. The input voltage is 1 / 4vmax. The DAC is controlled by a digital output, so it starts with the output Vmax. The difference between Vmax and input (1 / 4vmax) is – 3 / 4vmax, which is input to the integrator. As we can see, this negative voltage causes the integrator to produce a steep negative curve.

At the next clock, since X3 is negative, the output of X4 position is 0. It is latched, so that the DAC now outputs 0 voltage, and the voltage difference at x2 position is only + 1 / 4vmax. As we can see, this smaller positive curve needs to go through multiple cycles before exceeding the comparator threshold. The positive integral keeps the positive curve until the next clock cycle, then latches a 1 to the output, and we return to the original beginning.

If we look ΔΣ According to the frequency response of the modulator, we can see that the response characteristics can be summarized into the following formula: (the formula is omitted)

It can be seen that at low frequency, the output is equal to the input (x), while at high frequency, the output is equal to the quantization noise generating the noise spectrum as shown in Fig. 2.

ΔΣ The converter uses oversampling to disperse quantization noise in multiple frequency bands ΔΣ The modulator shapes the noise together so that most of the noise is not included in the signal measurement band. The noise shaping function enables the low-pass digital filter to eliminate most of the noise and produce high-precision voltage measurement.

Figure 2 noise spectrum

The output of the modulator enters a digital filter in which the response is adjusted according to the filter type or the number of samples. The final output data rate is determined by the following formula: data rate = modulation clock ÷ sampling rate.


One advantage of ADC is that noise is expressed as the ratio of full range (FS) signal to true RMS noise, which is expressed as significant bits (ENOB). For the 24 bit converter, we use the standard deviation (s) of the number of output codes to produce the following formula: (the formula is omitted)

Solving ENOB: (formula omitted)

ENOB = 24 - log2(s)

Alternatively, if the signal-to-noise ratio (SNR) is measured in dB, we can use the following formula:

ENOB = (SNRmeasdB – 1.76dB)/6.02dB

ΔΣ The commonly used filter type in the converter is sinc filter. They have deep attenuation grooves and multiple data rates at the output data rate, which means that a data rate of 60Hz can effectively eliminate any 60Hz signal from the measurement, and a data rate of 10Hz can eliminate both 50Hz and 60Hz signals.

You can adjust the ratio of the frequency of the input sampling rate to the output data rate. This sampling rate directly affects the number of significant bits (ENOB). With the increase of input sampling and output result ratio, ENOB can be improved and ADC resolution can be effectively improved.

Figure 3: comparison of MSC1210 ENOB and modulation decimation rate

Some ΔΣ The converter has a fixed data output rate, which can only be adjusted in a small range, while in other such converters, it allows flexible adjustment of the sampling rate by adjusting the modulator clock rate. When using 8051 microprocessor (in MSC1210 of Ti), the adjustment of these parameters can be controlled more flexibly. We can easily adjust and evaluate the performance of the converter in various modulation clocks and sampling rates. Each line (see Figure 3) represents a different clock rate, while the points on the line represent sampling rates 2020, 500, 255, 50, 20 and 10. Please note that the measurement of ENOB is mainly determined by the decimation rate, and the specific performance level can be changed by adjusting the modulation clock. As expected, the ENOB performance with the highest sampling rate decreases at the highest modulation clock rate.

So this leads to the problem that if the performance is not different at different clock rates, why don’t we always use the highest rate to obtain faster data conversion results? One reason is that as the clock rate increases, the power consumption of CMOS circuits will rise sharply.

If the power consumption is not a problem, the average number of samples can be obtained at a faster output rate, so as to further improve the performance level. This is easy to implement in MSC1210 with 32-bit accumulator, which can set and average 256 samples without processor intervention.

Input impedance and chopper stability

Ke Ba ΔΣ The analog input of the converter is regarded as a switch and capacitor. The equivalent result of the switching frequency is that a resistor is continuously connected to the internal capacitor, so the input impedance of the converter is directly related to the switching frequency. For MSC1210, the input impedance is as follows: (the formula is omitted)

If the sampling rate is 15.625 kHz and PGA is 1, the input impedance is 5MW. Higher sampling rate and PGA value will reduce this value. In order to eliminate this effect, many ΔΣ The converter provides an on-chip buffer. Even with buffers, there are still some obstacles to providing high DC precision input signal sampling.

Programmable gain amplifier (PGA)

Many ΔΣ Converters provide on-chip PGA, but they do not provide the same or expected effect. Some high gain results are just the drift of digital data, or multiplied by 2, which is basically of no benefit. These facts can be seen by careful examination of the data sheet. If increasing PGA by factor 2 can also reduce ENOB, there is no actual net gain, and it only means that the noise covers more output levels.

In some cases, a smaller reference voltage can be used to improve the gain, because the reference voltage determines the FS signal range. Reducing the reference voltage by 50% can make the input signal gain 2, but this increase in gain will lead to the noise limit of low reference voltage.

Establishment time

Setup time is another factor affecting data throughput in multi-channel systems. For high performance, ΔΣ The converter usually adopts FIR filter, such as sinc3 filter. Its advantage is that the signal delay is fixed in the whole filter, and it is easy to adjust, so as to adopt more delayed sampling stages to achieve variable sampling level. In the case of more filtering stages, the output data rate is low, and a sinc3 filter needs three conversion cycles to fully achieve the expected accuracy.

The establishment time will lead to the establishment error of the first few samples after channel switching. This problem has been solved in MSC1210 by using three filters and the automatic mode that can select the best filter after channel switching. For the first two samples after changing the multiplexer, the fastest filter is used, then sinc2 filter is used, and finally sinc3 filter is used for all samples. In this way, all conversion results can be completely established.

For multiplexed data systems, one way to solve the problem of setup time is to use a much faster data rate and average the output. For example, assuming that you want to use a 60Hz data output rate to obtain the advantage of 60Hz attenuation filtering, you can use a 240Hz sampling rate and average four sampling values to obtain the final 60Hz data rate. The advantage is that the current filter establishment time has been reduced from four samples at 60Hz (non synchronous channel switching) (66.6ms) to four samples at 240Hz (16.6ms). The setup time is now a sampling period of 60Hz data rate, while retaining the advantages of 60Hz attenuation filter. In MSC1210, a 32-bit accumulator is set to calculate the average value of four samples and discard the first result after channel switching (assuming that the channel switching is synchronized with the 60Hz output rate).


In the data acquisition system, two kinds of filter responses are mainly used: flat passband and sinc. The flat passband filter has a low attenuation reaching the cut-off frequency, followed by a large suppression band attenuation until the Nyquist frequency is reached. This makes it easier to design anti aliasing filters because the Nyquist frequency is usually 64 times higher than the off frequency. All that is needed may be a simple R-C filter.

Figure 4: sinc filter lobe

Other types of filters, such as sinc filters, do not provide the same high attenuation from the data rate to the Nyquist frequency (see Fig. 3) and multiple lobes after the sampling rate. If you want to achieve 100dB suppression band attenuation, you must design a filter to filter out the frequency components whose sinc filter attenuation is reduced by 40dB. However, when designing anti aliasing filters, it is important to keep in mind that high-frequency signals are not full amplitude. If the expected aliasing signal element has reached the highest level of – 20dB, in order to achieve 100dB attenuation of sinc filter (see Fig. 4), the anti aliasing filter only needs to be reduced by 40dB. This is because the sinc filter provides 40dB, assuming that the signal reaches the maximum value of – 20dB, which means that the anti aliasing filter only needs to add an additional 40dB attenuation. However, this is still an important requirement if you want the passband to contain frequencies close to the data rate.


For ultra-low frequencies, there are multiple noise sources, one of which is called 1 / f noise. Input chopping can eliminate most of this noise, but there are still other factors that can cause low-frequency drift in high-performance systems. Attention must be paid to how to weld components on the board to avoid mechanical stress, thermal gradient, thermocouple node and package orientation, which can affect the signal quality as drift. Techniques such as Allen variables can be used to observe these effects and analyze the success of eliminating them from the system.

Responsible editor: GT

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